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[binutils-gdb] opcodes: add support for eBPF
- From: Jose E.Marchesi <jemarch at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 23 May 2019 17:43:04 -0000
- Subject: [binutils-gdb] opcodes: add support for eBPF
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=79472b45328232b083e897a511d4160a6dde0463
commit 79472b45328232b083e897a511d4160a6dde0463
Author: Jose E. Marchesi <jose.marchesi@oracle.com>
Date: Thu May 23 19:04:36 2019 +0200
opcodes: add support for eBPF
This patch adds support for the Linux kernel eBPF architecture to the
opcodes. The port is based on CGEN.
opcodes/ChangeLog:
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
* configure: Regenerated.
* Makefile.am: Add rules for the files generated from cpu/bpf.cpu
and cpu/bpf.opc.
(HFILES): Add bpf-desc.h and bpf-opc.h.
(TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
bpf-ibld.c and bpf-opc.c.
(BPF_DEPS): Define.
* Makefile.in: Regenerated.
* disassemble.c (ARCH_bpf): Define.
(disassembler): Add case for bfd_arch_bpf.
(disassemble_init_for_target): Likewise.
(enum epbf_isa_attr): Define.
* disassemble.h: extern print_insn_bpf.
* bpf-asm.c: Generated.
* bpf-opc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-ibld.c: Likewise.
* bpf-dis.c: Likewise.
* bpf-desc.h: Likewise.
* bpf-desc.c: Likewise.
Diff:
---
opcodes/ChangeLog | 24 +
opcodes/Makefile.am | 17 +
opcodes/Makefile.in | 23 +
opcodes/bpf-asm.c | 590 ++++++++++++++++++
opcodes/bpf-desc.c | 1638 +++++++++++++++++++++++++++++++++++++++++++++++++
opcodes/bpf-desc.h | 266 ++++++++
opcodes/bpf-dis.c | 624 +++++++++++++++++++
opcodes/bpf-ibld.c | 956 +++++++++++++++++++++++++++++
opcodes/bpf-opc.c | 1495 ++++++++++++++++++++++++++++++++++++++++++++
opcodes/bpf-opc.h | 151 +++++
opcodes/configure | 19 +-
opcodes/configure.ac | 1 +
opcodes/disassemble.c | 35 ++
opcodes/disassemble.h | 1 +
14 files changed, 5837 insertions(+), 3 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3964e74..7853ffa 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,27 @@
+2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
+ * configure: Regenerated.
+ * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
+ and cpu/bpf.opc.
+ (HFILES): Add bpf-desc.h and bpf-opc.h.
+ (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
+ bpf-ibld.c and bpf-opc.c.
+ (BPF_DEPS): Define.
+ * Makefile.in: Regenerated.
+ * disassemble.c (ARCH_bpf): Define.
+ (disassembler): Add case for bfd_arch_bpf.
+ (disassemble_init_for_target): Likewise.
+ (enum epbf_isa_attr): Define.
+ * disassemble.h: extern print_insn_bpf.
+ * bpf-asm.c: Generated.
+ * bpf-opc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-ibld.c: Likewise.
+ * bpf-dis.c: Likewise.
+ * bpf-desc.h: Likewise.
+ * bpf-desc.c: Likewise.
+
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (coprocessor_opcodes): New instructions for VMRS
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 458a2b5..20a8a8d 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -59,6 +59,7 @@ BUILD_LIB_DEPS = @BUILD_LIB_DEPS@
# Header files.
HFILES = \
aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
+ bpf-desc.h bpf-opc.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
@@ -117,6 +118,11 @@ TARGET_LIBOPCODES_CFILES = \
d30v-dis.c \
d30v-opc.c \
dlx-dis.c \
+ bpf-asm.c \
+ bpf-desc.c \
+ bpf-dis.c \
+ bpf-ibld.c \
+ bpf-opc.c \
epiphany-asm.c \
epiphany-desc.c \
epiphany-dis.c \
@@ -370,6 +376,7 @@ CGENDEPS = \
CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16
if CGEN_MAINT
+BPF_DEPS = stamp-bpf
EPIPHANY_DEPS = stamp-epiphany
FR30_DEPS = stamp-fr30
FRV_DEPS = stamp-frv
@@ -384,6 +391,7 @@ OR1K_DEPS = stamp-or1k
XC16X_DEPS = stamp-xc16x
XSTORMY16_DEPS = stamp-xstormy16
else
+BPF_DEPS =
EPIPHANY_DEPS =
FR30_DEPS =
FRV_DEPS =
@@ -416,6 +424,15 @@ run-cgen-all:
# For now, require developers to configure with --enable-cgen-maint.
+$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \
+ $(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \
+ $(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)
+ @true
+
+stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc
+ $(MAKE) run-cgen arch=bpf prefix=bpf \
+ archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc
+
$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \
$(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \
$(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 3277ba9..ee8b311 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -408,6 +408,7 @@ pdfdir = @pdfdir@
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
+runstatedir = @runstatedir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
srcdir = @srcdir@
@@ -448,6 +449,7 @@ BFD_H = ../bfd/bfd.h
# Header files.
HFILES = \
aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
+ bpf-desc.h bpf-opc.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
frv-desc.h frv-opc.h \
@@ -507,6 +509,11 @@ TARGET_LIBOPCODES_CFILES = \
d30v-dis.c \
d30v-opc.c \
dlx-dis.c \
+ bpf-asm.c \
+ bpf-desc.c \
+ bpf-dis.c \
+ bpf-ibld.c \
+ bpf-opc.c \
epiphany-asm.c \
epiphany-desc.c \
epiphany-dis.c \
@@ -725,6 +732,8 @@ CGENDEPS = \
cgen-asm.in cgen-dis.in cgen-ibld.in
CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16
+@CGEN_MAINT_FALSE@BPF_DEPS =
+@CGEN_MAINT_TRUE@BPF_DEPS = stamp-bpf
@CGEN_MAINT_FALSE@EPIPHANY_DEPS =
@CGEN_MAINT_TRUE@EPIPHANY_DEPS = stamp-epiphany
@CGEN_MAINT_FALSE@FR30_DEPS =
@@ -897,6 +906,11 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avr-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfin-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-asm.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-desc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-dis.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-ibld.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-asm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-bitset.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-dis.Plo@am__quote@
@@ -1398,6 +1412,15 @@ run-cgen-all:
# For now, require developers to configure with --enable-cgen-maint.
+$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \
+ $(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \
+ $(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)
+ @true
+
+stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc
+ $(MAKE) run-cgen arch=bpf prefix=bpf \
+ archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc
+
$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \
$(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \
$(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \
diff --git a/opcodes/bpf-asm.c b/opcodes/bpf-asm.c
new file mode 100644
index 0000000..4332edc
--- /dev/null
+++ b/opcodes/bpf-asm.c
@@ -0,0 +1,590 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* Assembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+ THIS FILE IS MACHINE GENERATED WITH CGEN.
+ - the resultant file is machine generated, cgen-asm.in isn't
+
+ Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "bpf-desc.h"
+#include "bpf-opc.h"
+#include "opintl.h"
+#include "xregex.h"
+#include "libiberty.h"
+#include "safe-ctype.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+static const char * parse_insn_normal
+ (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
+
+/* -- assembler routines inserted here. */
+
+/* -- asm.c */
+
+/* Parse a signed 64-bit immediate. */
+
+static const char *
+parse_imm64 (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ int64_t *valuep)
+{
+ bfd_vma value;
+ enum cgen_parse_operand_result result;
+ const char *errmsg;
+
+ errmsg = (* cd->parse_operand_fn)
+ (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
+ &result, &value);
+ if (!errmsg)
+ *valuep = value;
+
+ return errmsg;
+}
+
+/* Endianness size operands are integer immediates whose values can be
+ 16, 32 or 64. */
+
+static const char *
+parse_endsize (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ unsigned long *valuep)
+{
+ const char *errmsg;
+
+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+ if (errmsg)
+ return errmsg;
+
+ switch (*valuep)
+ {
+ case 16:
+ case 32:
+ case 64:
+ break;
+ default:
+ return _("expected 16, 32 or 64 in");
+ }
+
+ return NULL;
+}
+
+/* Special check to ensure that the right instruction variant is used
+ for the given endianness induced by the ISA selected in the CPU.
+ See bpf.cpu for a discussion on how eBPF is really two instruction
+ sets. */
+
+int
+bpf_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+ CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
+
+ return cgen_bitset_intersect_p (&isas, cd->isas);
+}
+
+
+/* -- dis.c */
+
+const char * bpf_cgen_parse_operand
+ (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
+
+/* Main entry point for operand parsing.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers. */
+
+const char *
+bpf_cgen_parse_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ const char ** strp,
+ CGEN_FIELDS * fields)
+{
+ const char * errmsg = NULL;
+ /* Used by scalar operands that still need to be parsed. */
+ long junk ATTRIBUTE_UNUSED;
+
+ switch (opindex)
+ {
+ case BPF_OPERAND_DISP16 :
+ errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_DISP16, (long *) (& fields->f_offset16));
+ break;
+ case BPF_OPERAND_DISP32 :
+ errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_DISP32, (long *) (& fields->f_imm32));
+ break;
+ case BPF_OPERAND_DSTBE :
+ errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_dstbe);
+ break;
+ case BPF_OPERAND_DSTLE :
+ errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_dstle);
+ break;
+ case BPF_OPERAND_ENDSIZE :
+ errmsg = parse_endsize (cd, strp, BPF_OPERAND_ENDSIZE, (unsigned long *) (& fields->f_imm32));
+ break;
+ case BPF_OPERAND_IMM32 :
+ errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_IMM32, (long *) (& fields->f_imm32));
+ break;
+ case BPF_OPERAND_IMM64 :
+ errmsg = parse_imm64 (cd, strp, BPF_OPERAND_IMM64, (int64_t *) (& fields->f_imm64));
+ break;
+ case BPF_OPERAND_OFFSET16 :
+ errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_OFFSET16, (long *) (& fields->f_offset16));
+ break;
+ case BPF_OPERAND_SRCBE :
+ errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_srcbe);
+ break;
+ case BPF_OPERAND_SRCLE :
+ errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_srcle);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while parsing"),
+ opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+cgen_parse_fn * const bpf_cgen_parse_handlers[] =
+{
+ parse_insn_normal,
+};
+
+void
+bpf_cgen_init_asm (CGEN_CPU_DESC cd)
+{
+ bpf_cgen_init_opcode_table (cd);
+ bpf_cgen_init_ibld_table (cd);
+ cd->parse_handlers = & bpf_cgen_parse_handlers[0];
+ cd->parse_operand = bpf_cgen_parse_operand;
+#ifdef CGEN_ASM_INIT_HOOK
+CGEN_ASM_INIT_HOOK
+#endif
+}
+
+
+
+/* Regex construction routine.
+
+ This translates an opcode syntax string into a regex string,
+ by replacing any non-character syntax element (such as an
+ opcode) with the pattern '.*'
+
+ It then compiles the regex and stores it in the opcode, for
+ later use by bpf_cgen_assemble_insn
+
+ Returns NULL for success, an error message for failure. */
+
+char *
+bpf_cgen_build_insn_regex (CGEN_INSN *insn)
+{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+ char *rx = rxbuf;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+ int reg_err;
+
+ syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
+
+ /* Mnemonics come first in the syntax string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ return _("missing mnemonic in syntax string");
+ ++syn;
+
+ /* Generate a case sensitive regular expression that emulates case
+ insensitive matching in the "C" locale. We cannot generate a case
+ insensitive regular expression because in Turkish locales, 'i' and 'I'
+ are not equal modulo case conversion. */
+
+ /* Copy the literal mnemonic out of the insn. */
+ for (; *mnem; mnem++)
+ {
+ char c = *mnem;
+
+ if (ISALPHA (c))
+ {
+ *rx++ = '[';
+ *rx++ = TOLOWER (c);
+ *rx++ = TOUPPER (c);
+ *rx++ = ']';
+ }
+ else
+ *rx++ = c;
+ }
+
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
+
+#ifdef CGEN_ESCAPE_EXTENDED_REGEX
+ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+#endif
+ *rx++ = '\\';
+ *rx++ = c;
+ break;
+
+ default:
+ if (ISALPHA (c))
+ {
+ *rx++ = '[';
+ *rx++ = TOLOWER (c);
+ *rx++ = TOUPPER (c);
+ *rx++ = ']';
+ }
+ else
+ *rx++ = c;
+ break;
+ }
+ }
+ else
+ {
+ /* Replace non-syntax fields with globs. */
+ *rx++ = '.';
+ *rx++ = '*';
+ }
+ }
+
+ /* Trailing whitespace ok. */
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
+
+ /* But anchor it after that. */
+ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+ if (reg_err == 0)
+ return NULL;
+ else
+ {
+ static char msg[80];
+
+ regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
+ regfree ((regex_t *) CGEN_INSN_RX (insn));
+ free (CGEN_INSN_RX (insn));
+ (CGEN_INSN_RX (insn)) = NULL;
+ return msg;
+ }
+}
+
+
+/* Default insn parser.
+
+ The syntax string is scanned and operands are parsed and stored in FIELDS.
+ Relocs are queued as we go via other callbacks.
+
+ ??? Note that this is currently an all-or-nothing parser. If we fail to
+ parse the instruction, we return 0 and the caller will start over from
+ the beginning. Backtracking will be necessary in parsing subexpressions,
+ but that can be handled there. Not handling backtracking here may get
+ expensive in the case of the m68k. Deal with later.
+
+ Returns NULL for success, an error message for failure. */
+
+static const char *
+parse_insn_normal (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn,
+ const char **strp,
+ CGEN_FIELDS *fields)
+{
+ /* ??? Runtime added insns not handled yet. */
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const char *str = *strp;
+ const char *errmsg;
+ const char *p;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+ /* FIXME: wip */
+ int past_opcode_p;
+#endif
+
+ /* For now we assume the mnemonic is first (there are no leading operands).
+ We can parse it without needing to set up operand parsing.
+ GAS's input scrubber will ensure mnemonics are lowercase, but we may
+ not be called from GAS. */
+ p = CGEN_INSN_MNEMONIC (insn);
+ while (*p && TOLOWER (*p) == TOLOWER (*str))
+ ++p, ++str;
+
+ if (* p)
+ return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+ if (* str && ! ISSPACE (* str))
+ return _("unrecognized instruction");
+#endif
+
+ CGEN_INIT_PARSE (cd);
+ cgen_init_parse_operand (cd);
+#ifdef CGEN_MNEMONIC_OPERANDS
+ past_opcode_p = 0;
+#endif
+
+ /* We don't check for (*str != '\0') here because we want to parse
+ any trailing fake arguments in the syntax string. */
+ syn = CGEN_SYNTAX_STRING (syntax);
+
+ /* Mnemonics come first for now, ensure valid string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ abort ();
+
+ ++syn;
+
+ while (* syn != 0)
+ {
+ /* Non operand chars must match exactly. */
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ /* FIXME: While we allow for non-GAS callers above, we assume the
+ first char after the mnemonic part is a space. */
+ /* FIXME: We also take inappropriate advantage of the fact that
+ GAS's input scrubber will remove extraneous blanks. */
+ if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+ {
+#ifdef CGEN_MNEMONIC_OPERANDS
+ if (CGEN_SYNTAX_CHAR(* syn) == ' ')
+ past_opcode_p = 1;
+#endif
+ ++ syn;
+ ++ str;
+ }
+ else if (*str)
+ {
+ /* Syntax char didn't match. Can't be this insn. */
+ static char msg [80];
+
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
+ CGEN_SYNTAX_CHAR(*syn), *str);
+ return msg;
+ }
+ else
+ {
+ /* Ran out of input. */
+ static char msg [80];
+
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
+ CGEN_SYNTAX_CHAR(*syn));
+ return msg;
+ }
+ continue;
+ }
+
+#ifdef CGEN_MNEMONIC_OPERANDS
+ (void) past_opcode_p;
+#endif
+ /* We have an operand of some sort. */
+ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields);
+ if (errmsg)
+ return errmsg;
+
+ /* Done with this operand, continue with next one. */
+ ++ syn;
+ }
+
+ /* If we're at the end of the syntax string, we're done. */
+ if (* syn == 0)
+ {
+ /* FIXME: For the moment we assume a valid `str' can only contain
+ blanks now. IE: We needn't try again with a longer version of
+ the insn and it is assumed that longer versions of insns appear
+ before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
+ while (ISSPACE (* str))
+ ++ str;
+
+ if (* str != '\0')
+ return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+ return NULL;
+ }
+
+ /* We couldn't parse it. */
+ return _("unrecognized instruction");
+}
+
+/* Main entry point.
+ This routine is called for each instruction to be assembled.
+ STR points to the insn to be assembled.
+ We assume all necessary tables have been initialized.
+ The assembled instruction, less any fixups, is stored in BUF.
+ Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+ still needs to be converted to target byte order, otherwise BUF is an array
+ of bytes in target byte order.
+ The result is a pointer to the insn's entry in the opcode table,
+ or NULL if an error occured (an error message will have already been
+ printed).
+
+ Note that when processing (non-alias) macro-insns,
+ this function recurses.
+
+ ??? It's possible to make this cpu-independent.
+ One would have to deal with a few minor things.
+ At this point in time doing so would be more of a curiosity than useful
+ [for example this file isn't _that_ big], but keeping the possibility in
+ mind helps keep the design clean. */
+
+const CGEN_INSN *
+bpf_cgen_assemble_insn (CGEN_CPU_DESC cd,
+ const char *str,
+ CGEN_FIELDS *fields,
+ CGEN_INSN_BYTES_PTR buf,
+ char **errmsg)
+{
+ const char *start;
+ CGEN_INSN_LIST *ilist;
+ const char *parse_errmsg = NULL;
+ const char *insert_errmsg = NULL;
+ int recognized_mnemonic = 0;
+
+ /* Skip leading white space. */
+ while (ISSPACE (* str))
+ ++ str;
+
+ /* The instructions are stored in hashed lists.
+ Get the first in the list. */
+ ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
+
+ /* Keep looking until we find a match. */
+ start = str;
+ for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+ {
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+ if (! bpf_cgen_insn_supported (cd, insn))
+ continue;
+#endif
+ /* If the RELAXED attribute is set, this is an insn that shouldn't be
+ chosen immediately. Instead, it is used during assembler/linker
+ relaxation if possible. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
+ continue;
+
+ str = start;
+
+ /* Skip this insn if str doesn't look right lexically. */
+ if (CGEN_INSN_RX (insn) != NULL &&
+ regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+ continue;
+
+ /* Allow parse/insert handlers to obtain length of insn. */
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+ if (parse_errmsg != NULL)
+ continue;
+
+ /* ??? 0 is passed for `pc'. */
+ insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+ (bfd_vma) 0);
+ if (insert_errmsg != NULL)
+ continue;
+
+ /* It is up to the caller to actually output the insn and any
+ queued relocs. */
+ return insn;
+ }
+
+ {
+ static char errbuf[150];
+ const char *tmp_errmsg;
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+#define be_verbose 1
+#else
+#define be_verbose 0
+#endif
+
+ if (be_verbose)
+ {
+ /* If requesting verbose error messages, use insert_errmsg.
+ Failing that, use parse_errmsg. */
+ tmp_errmsg = (insert_errmsg ? insert_errmsg :
+ parse_errmsg ? parse_errmsg :
+ recognized_mnemonic ?
+ _("unrecognized form of instruction") :
+ _("unrecognized instruction"));
+
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+ }
+ else
+ {
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+ }
+
+ *errmsg = errbuf;
+ return NULL;
+ }
+}
diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c
new file mode 100644
index 0000000..4c94723
--- /dev/null
+++ b/opcodes/bpf-desc.c
@@ -0,0 +1,1638 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* CPU data for bpf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "bpf-desc.h"
+#include "bpf-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+#include "xregex.h"
+
+/* Attributes. */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+ { "#f", 0 },
+ { "#t", 1 },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
+{
+ { "base", MACH_BASE },
+ { "bpf", MACH_BPF },
+ { "max", MACH_MAX },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
+{
+ { "ebpfle", ISA_EBPFLE },
+ { "ebpfbe", ISA_EBPFBE },
+ { "max", ISA_MAX },
+ { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "RESERVED", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "PC", &bool_attr[0], &bool_attr[0] },
+ { "PROFILE", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "ALIAS", &bool_attr[0], &bool_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+ { "RELAXED", &bool_attr[0], &bool_attr[0] },
+ { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+ { "PBB", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+/* Instruction set variants. */
+
+static const CGEN_ISA bpf_cgen_isa_table[] = {
+ { "ebpfle", 64, 8, 64, 128 },
+ { "ebpfbe", 64, 8, 64, 128 },
+ { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants. */
+
+static const CGEN_MACH bpf_cgen_mach_table[] = {
+ { "bpf", "bpf", MACH_BPF, 0 },
+ { 0, 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] =
+{
+ { "%a", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "%ctx", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "%fp", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r10", 10, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD bpf_cgen_opval_h_gpr =
+{
+ & bpf_cgen_opval_h_gpr_entries[0],
+ 14,
+ 0, 0, 0, 0, ""
+};
+
+
+/* The hardware table. */
+
+#define A(a) (1 << CGEN_HW_##a)
+
+const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
+{
+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF), 0 } }, { { 1, "\xc0" } } } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+ { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
+};
+
+#undef A
+
+
+/* The instruction field table. */
+
+#define A(a) (1 << CGEN_IFLD_##a)
+
+const CGEN_IFLD bpf_cgen_ifld_table[] =
+{
+ { BPF_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OP_CODE, "f-op-code", 0, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OP_SRC, "f-op-src", 0, 8, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+ { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+ { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
+ { BPF_F_SRCBE, "f-srcbe", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
+ { BPF_F_REGS, "f-regs", 8, 8, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_OFFSET16, "f-offset16", 16, 16, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_IMM32, "f-imm32", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_IMM64_A, "f-imm64-a", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_IMM64_B, "f-imm64-b", 64, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_IMM64_C, "f-imm64-c", 96, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { BPF_F_IMM64, "f-imm64", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+ { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
+};
+
+#undef A
+
+
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_A] } },
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_B] } },
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_C] } },
+ { 0, { (const PTR) 0 } }
+};
+
+/* The operand table. */
+
+#define A(a) (1 << CGEN_OPERAND_##a)
+#define OPERAND(op) BPF_OPERAND_##op
+
+const CGEN_OPERAND bpf_cgen_operand_table[] =
+{
+/* pc: program counter */
+ { "pc", BPF_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_NIL] } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* dstle: destination register */
+ { "dstle", BPF_OPERAND_DSTLE, HW_H_GPR, 3, 4,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTLE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+/* srcle: source register */
+ { "srcle", BPF_OPERAND_SRCLE, HW_H_GPR, 7, 4,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCLE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+/* dstbe: destination register */
+ { "dstbe", BPF_OPERAND_DSTBE, HW_H_GPR, 7, 4,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTBE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
+/* srcbe: source register */
+ { "srcbe", BPF_OPERAND_SRCBE, HW_H_GPR, 3, 4,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCBE] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } },
+/* disp16: 16-bit PC-relative address */
+ { "disp16", BPF_OPERAND_DISP16, HW_H_SINT, 15, 16,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* disp32: 32-bit PC-relative address */
+ { "disp32", BPF_OPERAND_DISP32, HW_H_SINT, 31, 32,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* imm32: 32-bit immediate */
+ { "imm32", BPF_OPERAND_IMM32, HW_H_SINT, 31, 32,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* offset16: 16-bit offset */
+ { "offset16", BPF_OPERAND_OFFSET16, HW_H_SINT, 15, 16,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* imm64: 64-bit immediate */
+ { "imm64", BPF_OPERAND_IMM64, HW_H_SINT64, 31, 96,
+ { 3, { (const PTR) &BPF_F_IMM64_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* endsize: endianness size immediate: 16, 32 or 64 */
+ { "endsize", BPF_OPERAND_ENDSIZE, HW_H_UINT, 31, 32,
+ { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+/* sentinel */
+ { 0, 0, 0, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
+};
+
+#undef A
+
+
+/* The instruction table. */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#define A(a) (1 << CGEN_INSN_##a)
+
+static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+/* add $dstle,$imm32 */
+ {
+ BPF_INSN_ADDILE, "addile", "add", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* add $dstle,$srcle */
+ {
+ BPF_INSN_ADDRLE, "addrle", "add", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* add32 $dstle,$imm32 */
+ {
+ BPF_INSN_ADD32ILE, "add32ile", "add32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* add32 $dstle,$srcle */
+ {
+ BPF_INSN_ADD32RLE, "add32rle", "add32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* sub $dstle,$imm32 */
+ {
+ BPF_INSN_SUBILE, "subile", "sub", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* sub $dstle,$srcle */
+ {
+ BPF_INSN_SUBRLE, "subrle", "sub", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* sub32 $dstle,$imm32 */
+ {
+ BPF_INSN_SUB32ILE, "sub32ile", "sub32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* sub32 $dstle,$srcle */
+ {
+ BPF_INSN_SUB32RLE, "sub32rle", "sub32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mul $dstle,$imm32 */
+ {
+ BPF_INSN_MULILE, "mulile", "mul", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mul $dstle,$srcle */
+ {
+ BPF_INSN_MULRLE, "mulrle", "mul", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mul32 $dstle,$imm32 */
+ {
+ BPF_INSN_MUL32ILE, "mul32ile", "mul32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mul32 $dstle,$srcle */
+ {
+ BPF_INSN_MUL32RLE, "mul32rle", "mul32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* div $dstle,$imm32 */
+ {
+ BPF_INSN_DIVILE, "divile", "div", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* div $dstle,$srcle */
+ {
+ BPF_INSN_DIVRLE, "divrle", "div", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* div32 $dstle,$imm32 */
+ {
+ BPF_INSN_DIV32ILE, "div32ile", "div32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* div32 $dstle,$srcle */
+ {
+ BPF_INSN_DIV32RLE, "div32rle", "div32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* or $dstle,$imm32 */
+ {
+ BPF_INSN_ORILE, "orile", "or", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* or $dstle,$srcle */
+ {
+ BPF_INSN_ORRLE, "orrle", "or", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* or32 $dstle,$imm32 */
+ {
+ BPF_INSN_OR32ILE, "or32ile", "or32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* or32 $dstle,$srcle */
+ {
+ BPF_INSN_OR32RLE, "or32rle", "or32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* and $dstle,$imm32 */
+ {
+ BPF_INSN_ANDILE, "andile", "and", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* and $dstle,$srcle */
+ {
+ BPF_INSN_ANDRLE, "andrle", "and", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* and32 $dstle,$imm32 */
+ {
+ BPF_INSN_AND32ILE, "and32ile", "and32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* and32 $dstle,$srcle */
+ {
+ BPF_INSN_AND32RLE, "and32rle", "and32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* lsh $dstle,$imm32 */
+ {
+ BPF_INSN_LSHILE, "lshile", "lsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* lsh $dstle,$srcle */
+ {
+ BPF_INSN_LSHRLE, "lshrle", "lsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* lsh32 $dstle,$imm32 */
+ {
+ BPF_INSN_LSH32ILE, "lsh32ile", "lsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* lsh32 $dstle,$srcle */
+ {
+ BPF_INSN_LSH32RLE, "lsh32rle", "lsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* rsh $dstle,$imm32 */
+ {
+ BPF_INSN_RSHILE, "rshile", "rsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* rsh $dstle,$srcle */
+ {
+ BPF_INSN_RSHRLE, "rshrle", "rsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* rsh32 $dstle,$imm32 */
+ {
+ BPF_INSN_RSH32ILE, "rsh32ile", "rsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* rsh32 $dstle,$srcle */
+ {
+ BPF_INSN_RSH32RLE, "rsh32rle", "rsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mod $dstle,$imm32 */
+ {
+ BPF_INSN_MODILE, "modile", "mod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mod $dstle,$srcle */
+ {
+ BPF_INSN_MODRLE, "modrle", "mod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mod32 $dstle,$imm32 */
+ {
+ BPF_INSN_MOD32ILE, "mod32ile", "mod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mod32 $dstle,$srcle */
+ {
+ BPF_INSN_MOD32RLE, "mod32rle", "mod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xor $dstle,$imm32 */
+ {
+ BPF_INSN_XORILE, "xorile", "xor", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xor $dstle,$srcle */
+ {
+ BPF_INSN_XORRLE, "xorrle", "xor", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xor32 $dstle,$imm32 */
+ {
+ BPF_INSN_XOR32ILE, "xor32ile", "xor32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xor32 $dstle,$srcle */
+ {
+ BPF_INSN_XOR32RLE, "xor32rle", "xor32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov $dstle,$imm32 */
+ {
+ BPF_INSN_MOVILE, "movile", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov $dstle,$srcle */
+ {
+ BPF_INSN_MOVRLE, "movrle", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov32 $dstle,$imm32 */
+ {
+ BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov32 $dstle,$srcle */
+ {
+ BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* arsh $dstle,$imm32 */
+ {
+ BPF_INSN_ARSHILE, "arshile", "arsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* arsh $dstle,$srcle */
+ {
+ BPF_INSN_ARSHRLE, "arshrle", "arsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* arsh32 $dstle,$imm32 */
+ {
+ BPF_INSN_ARSH32ILE, "arsh32ile", "arsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* arsh32 $dstle,$srcle */
+ {
+ BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* neg $dstle */
+ {
+ BPF_INSN_NEGLE, "negle", "neg", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* neg32 $dstle */
+ {
+ BPF_INSN_NEG32LE, "neg32le", "neg32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* add $dstbe,$imm32 */
+ {
+ BPF_INSN_ADDIBE, "addibe", "add", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* add $dstbe,$srcbe */
+ {
+ BPF_INSN_ADDRBE, "addrbe", "add", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* add32 $dstbe,$imm32 */
+ {
+ BPF_INSN_ADD32IBE, "add32ibe", "add32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* add32 $dstbe,$srcbe */
+ {
+ BPF_INSN_ADD32RBE, "add32rbe", "add32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* sub $dstbe,$imm32 */
+ {
+ BPF_INSN_SUBIBE, "subibe", "sub", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* sub $dstbe,$srcbe */
+ {
+ BPF_INSN_SUBRBE, "subrbe", "sub", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* sub32 $dstbe,$imm32 */
+ {
+ BPF_INSN_SUB32IBE, "sub32ibe", "sub32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* sub32 $dstbe,$srcbe */
+ {
+ BPF_INSN_SUB32RBE, "sub32rbe", "sub32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mul $dstbe,$imm32 */
+ {
+ BPF_INSN_MULIBE, "mulibe", "mul", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mul $dstbe,$srcbe */
+ {
+ BPF_INSN_MULRBE, "mulrbe", "mul", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mul32 $dstbe,$imm32 */
+ {
+ BPF_INSN_MUL32IBE, "mul32ibe", "mul32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mul32 $dstbe,$srcbe */
+ {
+ BPF_INSN_MUL32RBE, "mul32rbe", "mul32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* div $dstbe,$imm32 */
+ {
+ BPF_INSN_DIVIBE, "divibe", "div", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* div $dstbe,$srcbe */
+ {
+ BPF_INSN_DIVRBE, "divrbe", "div", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* div32 $dstbe,$imm32 */
+ {
+ BPF_INSN_DIV32IBE, "div32ibe", "div32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* div32 $dstbe,$srcbe */
+ {
+ BPF_INSN_DIV32RBE, "div32rbe", "div32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* or $dstbe,$imm32 */
+ {
+ BPF_INSN_ORIBE, "oribe", "or", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* or $dstbe,$srcbe */
+ {
+ BPF_INSN_ORRBE, "orrbe", "or", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* or32 $dstbe,$imm32 */
+ {
+ BPF_INSN_OR32IBE, "or32ibe", "or32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* or32 $dstbe,$srcbe */
+ {
+ BPF_INSN_OR32RBE, "or32rbe", "or32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* and $dstbe,$imm32 */
+ {
+ BPF_INSN_ANDIBE, "andibe", "and", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* and $dstbe,$srcbe */
+ {
+ BPF_INSN_ANDRBE, "andrbe", "and", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* and32 $dstbe,$imm32 */
+ {
+ BPF_INSN_AND32IBE, "and32ibe", "and32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* and32 $dstbe,$srcbe */
+ {
+ BPF_INSN_AND32RBE, "and32rbe", "and32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* lsh $dstbe,$imm32 */
+ {
+ BPF_INSN_LSHIBE, "lshibe", "lsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* lsh $dstbe,$srcbe */
+ {
+ BPF_INSN_LSHRBE, "lshrbe", "lsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* lsh32 $dstbe,$imm32 */
+ {
+ BPF_INSN_LSH32IBE, "lsh32ibe", "lsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* lsh32 $dstbe,$srcbe */
+ {
+ BPF_INSN_LSH32RBE, "lsh32rbe", "lsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* rsh $dstbe,$imm32 */
+ {
+ BPF_INSN_RSHIBE, "rshibe", "rsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* rsh $dstbe,$srcbe */
+ {
+ BPF_INSN_RSHRBE, "rshrbe", "rsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* rsh32 $dstbe,$imm32 */
+ {
+ BPF_INSN_RSH32IBE, "rsh32ibe", "rsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* rsh32 $dstbe,$srcbe */
+ {
+ BPF_INSN_RSH32RBE, "rsh32rbe", "rsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mod $dstbe,$imm32 */
+ {
+ BPF_INSN_MODIBE, "modibe", "mod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mod $dstbe,$srcbe */
+ {
+ BPF_INSN_MODRBE, "modrbe", "mod", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mod32 $dstbe,$imm32 */
+ {
+ BPF_INSN_MOD32IBE, "mod32ibe", "mod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mod32 $dstbe,$srcbe */
+ {
+ BPF_INSN_MOD32RBE, "mod32rbe", "mod32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* xor $dstbe,$imm32 */
+ {
+ BPF_INSN_XORIBE, "xoribe", "xor", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* xor $dstbe,$srcbe */
+ {
+ BPF_INSN_XORRBE, "xorrbe", "xor", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* xor32 $dstbe,$imm32 */
+ {
+ BPF_INSN_XOR32IBE, "xor32ibe", "xor32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* xor32 $dstbe,$srcbe */
+ {
+ BPF_INSN_XOR32RBE, "xor32rbe", "xor32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov $dstbe,$imm32 */
+ {
+ BPF_INSN_MOVIBE, "movibe", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov $dstbe,$srcbe */
+ {
+ BPF_INSN_MOVRBE, "movrbe", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov32 $dstbe,$imm32 */
+ {
+ BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov32 $dstbe,$srcbe */
+ {
+ BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* arsh $dstbe,$imm32 */
+ {
+ BPF_INSN_ARSHIBE, "arshibe", "arsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* arsh $dstbe,$srcbe */
+ {
+ BPF_INSN_ARSHRBE, "arshrbe", "arsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* arsh32 $dstbe,$imm32 */
+ {
+ BPF_INSN_ARSH32IBE, "arsh32ibe", "arsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* arsh32 $dstbe,$srcbe */
+ {
+ BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* neg $dstbe */
+ {
+ BPF_INSN_NEGBE, "negbe", "neg", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* neg32 $dstbe */
+ {
+ BPF_INSN_NEG32BE, "neg32be", "neg32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* endle $dstle,$endsize */
+ {
+ BPF_INSN_ENDLELE, "endlele", "endle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* endbe $dstle,$endsize */
+ {
+ BPF_INSN_ENDBELE, "endbele", "endbe", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* endle $dstbe,$endsize */
+ {
+ BPF_INSN_ENDLEBE, "endlebe", "endle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* endbe $dstbe,$endsize */
+ {
+ BPF_INSN_ENDBEBE, "endbebe", "endbe", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* lddw $dstle,$imm64 */
+ {
+ BPF_INSN_LDDWLE, "lddwle", "lddw", 128,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* lddw $dstbe,$imm64 */
+ {
+ BPF_INSN_LDDWBE, "lddwbe", "lddw", 128,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldabsw $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDABSWLE, "ldabswle", "ldabsw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldabsh $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDABSHLE, "ldabshle", "ldabsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldabsb $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDABSBLE, "ldabsble", "ldabsb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldabsdw $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDABSDWLE, "ldabsdwle", "ldabsdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldindw $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDINDWLE, "ldindwle", "ldindw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldindh $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDINDHLE, "ldindhle", "ldindh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldindb $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDINDBLE, "ldindble", "ldindb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldinddw $dstle,$srcle,$imm32 */
+ {
+ BPF_INSN_LDINDDWLE, "ldinddwle", "ldinddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldabsw $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDABSWBE, "ldabswbe", "ldabsw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldabsh $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDABSHBE, "ldabshbe", "ldabsh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldabsb $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDABSBBE, "ldabsbbe", "ldabsb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldabsdw $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDABSDWBE, "ldabsdwbe", "ldabsdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldindw $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDINDWBE, "ldindwbe", "ldindw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldindh $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDINDHBE, "ldindhbe", "ldindh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldindb $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDINDBBE, "ldindbbe", "ldindb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldinddw $dstbe,$srcbe,$imm32 */
+ {
+ BPF_INSN_LDINDDWBE, "ldinddwbe", "ldinddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldxw $dstle,[$srcle+$offset16] */
+ {
+ BPF_INSN_LDXWLE, "ldxwle", "ldxw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldxh $dstle,[$srcle+$offset16] */
+ {
+ BPF_INSN_LDXHLE, "ldxhle", "ldxh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldxb $dstle,[$srcle+$offset16] */
+ {
+ BPF_INSN_LDXBLE, "ldxble", "ldxb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldxdw $dstle,[$srcle+$offset16] */
+ {
+ BPF_INSN_LDXDWLE, "ldxdwle", "ldxdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stxw [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_STXWLE, "stxwle", "stxw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stxh [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_STXHLE, "stxhle", "stxh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stxb [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_STXBLE, "stxble", "stxb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stxdw [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_STXDWLE, "stxdwle", "stxdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* ldxw $dstbe,[$srcbe+$offset16] */
+ {
+ BPF_INSN_LDXWBE, "ldxwbe", "ldxw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldxh $dstbe,[$srcbe+$offset16] */
+ {
+ BPF_INSN_LDXHBE, "ldxhbe", "ldxh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldxb $dstbe,[$srcbe+$offset16] */
+ {
+ BPF_INSN_LDXBBE, "ldxbbe", "ldxb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ldxdw $dstbe,[$srcbe+$offset16] */
+ {
+ BPF_INSN_LDXDWBE, "ldxdwbe", "ldxdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stxw [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_STXWBE, "stxwbe", "stxw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stxh [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_STXHBE, "stxhbe", "stxh", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stxb [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_STXBBE, "stxbbe", "stxb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stxdw [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_STXDWBE, "stxdwbe", "stxdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stb [$dstle+$offset16],$imm32 */
+ {
+ BPF_INSN_STBLE, "stble", "stb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* sth [$dstle+$offset16],$imm32 */
+ {
+ BPF_INSN_STHLE, "sthle", "sth", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stw [$dstle+$offset16],$imm32 */
+ {
+ BPF_INSN_STWLE, "stwle", "stw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stdw [$dstle+$offset16],$imm32 */
+ {
+ BPF_INSN_STDWLE, "stdwle", "stdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* stb [$dstbe+$offset16],$imm32 */
+ {
+ BPF_INSN_STBBE, "stbbe", "stb", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* sth [$dstbe+$offset16],$imm32 */
+ {
+ BPF_INSN_STHBE, "sthbe", "sth", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stw [$dstbe+$offset16],$imm32 */
+ {
+ BPF_INSN_STWBE, "stwbe", "stw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* stdw [$dstbe+$offset16],$imm32 */
+ {
+ BPF_INSN_STDWBE, "stdwbe", "stdw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jeq $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JEQILE, "jeqile", "jeq", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jeq $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JEQRLE, "jeqrle", "jeq", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jgt $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JGTILE, "jgtile", "jgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jgt $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JGTRLE, "jgtrle", "jgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jge $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JGEILE, "jgeile", "jge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jge $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JGERLE, "jgerle", "jge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jlt $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JLTILE, "jltile", "jlt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jlt $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JLTRLE, "jltrle", "jlt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jle $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JLEILE, "jleile", "jle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jle $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JLERLE, "jlerle", "jle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jset $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSETILE, "jsetile", "jset", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jset $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSETRLE, "jsetrle", "jset", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jne $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JNEILE, "jneile", "jne", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jne $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JNERLE, "jnerle", "jne", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsgt $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsgt $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsge $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGEILE, "jsgeile", "jsge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsge $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSGERLE, "jsgerle", "jsge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jslt $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLTILE, "jsltile", "jslt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jslt $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsle $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLEILE, "jsleile", "jsle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsle $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSLERLE, "jslerle", "jsle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jeq $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JEQIBE, "jeqibe", "jeq", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jeq $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jgt $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JGTIBE, "jgtibe", "jgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jgt $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jge $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JGEIBE, "jgeibe", "jge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jge $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JGERBE, "jgerbe", "jge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jlt $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JLTIBE, "jltibe", "jlt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jlt $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JLTRBE, "jltrbe", "jlt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jle $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JLEIBE, "jleibe", "jle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jle $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JLERBE, "jlerbe", "jle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jset $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSETIBE, "jsetibe", "jset", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jset $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSETRBE, "jsetrbe", "jset", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jne $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JNEIBE, "jneibe", "jne", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jne $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JNERBE, "jnerbe", "jne", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsgt $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsgt $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsge $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsge $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jslt $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jslt $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsle $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsle $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSLERBE, "jslerbe", "jsle", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ja $disp16 */
+ {
+ BPF_INSN_JA, "ja", "ja", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+ },
+/* call $disp32 */
+ {
+ BPF_INSN_CALL, "call", "call", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+ },
+/* exit */
+ {
+ BPF_INSN_EXIT, "exit", "exit", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+ },
+/* xadddw [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_XADDDWLE, "xadddwle", "xadddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xaddw [$dstle+$offset16],$srcle */
+ {
+ BPF_INSN_XADDWLE, "xaddwle", "xaddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* xadddw [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_XADDDWBE, "xadddwbe", "xadddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* xaddw [$dstbe+$offset16],$srcbe */
+ {
+ BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call. */
+
+static void
+init_tables (void)
+{
+}
+
+#ifndef opcodes_error_handler
+#define opcodes_error_handler(...) \
+ fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
+#endif
+
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table (CGEN_CPU_TABLE *);
+static void build_ifield_table (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table (CGEN_CPU_TABLE *);
+static void bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *);
+
+/* Subroutine of bpf_cgen_cpu_open to look up a mach via its bfd name. */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
+{
+ while (table->name)
+ {
+ if (strcmp (name, table->bfd_name) == 0)
+ return table;
+ ++table;
+ }
+ return NULL;
+}
+
+/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
+
+static void
+build_hw_table (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_HW_ENTRY *init = & bpf_cgen_hw_table[0];
+ /* MAX_HW is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_HW_ENTRY **selected =
+ (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+ cd->hw_table.init_entries = init;
+ cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+ memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+ /* ??? For now we just use machs to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->hw_table.entries = selected;
+ cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
+
+static void
+build_ifield_table (CGEN_CPU_TABLE *cd)
+{
+ cd->ifld_table = & bpf_cgen_ifld_table[0];
+}
+
+/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */
+
+static void
+build_operand_table (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_OPERAND *init = & bpf_cgen_operand_table[0];
+ /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
+
+ cd->operand_table.init_entries = init;
+ cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+ memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+ /* ??? For now we just use mach to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->operand_table.entries = selected;
+ cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of bpf_cgen_cpu_open to build the hardware table.
+ ??? This could leave out insns not supported by the specified mach/isa,
+ but that would cause errors like "foo only supported by bar" to become
+ "unknown insn", so for now we include all insns and require the app to
+ do the checking later.
+ ??? On the other hand, parsing of such insns may require their hardware or
+ operand elements to be in the table [which they mightn't be]. */
+
+static void
+build_insn_table (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ const CGEN_IBASE *ib = & bpf_cgen_insn_table[0];
+ CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+ memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+ for (i = 0; i < MAX_INSNS; ++i)
+ insns[i].base = &ib[i];
+ cd->insn_table.init_entries = insns;
+ cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of bpf_cgen_cpu_open to rebuild the tables. */
+
+static void
+bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
+{
+ int i;
+ CGEN_BITSET *isas = cd->isas;
+ unsigned int machs = cd->machs;
+
+ cd->int_insn_p = CGEN_INT_INSN_P;
+
+ /* Data derived from the isa spec. */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+ cd->default_insn_bitsize = UNSET;
+ cd->base_insn_bitsize = UNSET;
+ cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
+ cd->max_insn_bitsize = 0;
+ for (i = 0; i < MAX_ISAS; ++i)
+ if (cgen_bitset_contains (isas, i))
+ {
+ const CGEN_ISA *isa = & bpf_cgen_isa_table[i];
+
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
+ if (cd->default_insn_bitsize == UNSET)
+ cd->default_insn_bitsize = isa->default_insn_bitsize;
+ else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+ ; /* This is ok. */
+ else
+ cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
+ if (cd->base_insn_bitsize == UNSET)
+ cd->base_insn_bitsize = isa->base_insn_bitsize;
+ else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+ ; /* This is ok. */
+ else
+ cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Set min,max insn sizes. */
+ if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+ cd->min_insn_bitsize = isa->min_insn_bitsize;
+ if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+ cd->max_insn_bitsize = isa->max_insn_bitsize;
+ }
+
+ /* Data derived from the mach spec. */
+ for (i = 0; i < MAX_MACHS; ++i)
+ if (((1 << i) & machs) != 0)
+ {
+ const CGEN_MACH *mach = & bpf_cgen_mach_table[i];
+
+ if (mach->insn_chunk_bitsize != 0)
+ {
+ if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+ {
+ opcodes_error_handler
+ (/* xgettext:c-format */
+ _("internal error: bpf_cgen_rebuild_tables: "
+ "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
+ cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+ abort ();
+ }
+
+ cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+ }
+ }
+
+ /* Determine which hw elements are used by MACH. */
+ build_hw_table (cd);
+
+ /* Build the ifield table. */
+ build_ifield_table (cd);
+
+ /* Determine which operands are used by MACH/ISA. */
+ build_operand_table (cd);
+
+ /* Build the instruction table. */
+ build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+ It's much like opening a file, and must be the first function called.
+ The arguments are a set of (type/value) pairs, terminated with
+ CGEN_CPU_OPEN_END.
+
+ Currently supported values:
+ CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
+ CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
+ CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+ CGEN_CPU_OPEN_ENDIAN: specify endian choice
+ CGEN_CPU_OPEN_END: terminates arguments
+
+ ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+ precluded. */
+
+CGEN_CPU_DESC
+bpf_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+ CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+ static int init_p;
+ CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
+ unsigned int machs = 0; /* 0 = "unspecified" */
+ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+ va_list ap;
+
+ if (! init_p)
+ {
+ init_tables ();
+ init_p = 1;
+ }
+
+ memset (cd, 0, sizeof (*cd));
+
+ va_start (ap, arg_type);
+ while (arg_type != CGEN_CPU_OPEN_END)
+ {
+ switch (arg_type)
+ {
+ case CGEN_CPU_OPEN_ISAS :
+ isas = va_arg (ap, CGEN_BITSET *);
+ break;
+ case CGEN_CPU_OPEN_MACHS :
+ machs = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_BFDMACH :
+ {
+ const char *name = va_arg (ap, const char *);
+ const CGEN_MACH *mach =
+ lookup_mach_via_bfd_name (bpf_cgen_mach_table, name);
+
+ if (mach != NULL)
+ machs |= 1 << mach->num;
+ break;
+ }
+ case CGEN_CPU_OPEN_ENDIAN :
+ endian = va_arg (ap, enum cgen_endian);
+ break;
+ default :
+ opcodes_error_handler
+ (/* xgettext:c-format */
+ _("internal error: bpf_cgen_cpu_open: "
+ "unsupported argument `%d'"),
+ arg_type);
+ abort (); /* ??? return NULL? */
+ }
+ arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+ }
+ va_end (ap);
+
+ /* Mach unspecified means "all". */
+ if (machs == 0)
+ machs = (1 << MAX_MACHS) - 1;
+ /* Base mach is always selected. */
+ machs |= 1;
+ if (endian == CGEN_ENDIAN_UNKNOWN)
+ {
+ /* ??? If target has only one, could have a default. */
+ opcodes_error_handler
+ (/* xgettext:c-format */
+ _("internal error: bpf_cgen_cpu_open: no endianness specified"));
+ abort ();
+ }
+
+ cd->isas = cgen_bitset_copy (isas);
+ cd->machs = machs;
+ cd->endian = endian;
+ /* FIXME: for the sparc case we can determine insn-endianness statically.
+ The worry here is where both data and insn endian can be independently
+ chosen, in which case this function will need another argument.
+ Actually, will want to allow for more arguments in the future anyway. */
+ cd->insn_endian = endian;
+
+ /* Table (re)builder. */
+ cd->rebuild_tables = bpf_cgen_rebuild_tables;
+ bpf_cgen_rebuild_tables (cd);
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+
+ return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to bpf_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+ MACH_NAME is the bfd name of the mach. */
+
+CGEN_CPU_DESC
+bpf_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
+{
+ return bpf_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, endian,
+ CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+ ??? This can live in a machine independent file, but there's currently
+ no place to put this file (there's no libcgen). libopcodes is the wrong
+ place as some simulator ports use this but they don't use libopcodes. */
+
+void
+bpf_cgen_cpu_close (CGEN_CPU_DESC cd)
+{
+ unsigned int i;
+ const CGEN_INSN *insns;
+
+ if (cd->macro_insn_table.init_entries)
+ {
+ insns = cd->macro_insn_table.init_entries;
+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX ((insns)))
+ regfree (CGEN_INSN_RX (insns));
+ }
+
+ if (cd->insn_table.init_entries)
+ {
+ insns = cd->insn_table.init_entries;
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+ }
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+ if (cd->insn_table.init_entries)
+ free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+ if (cd->hw_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
+ free (cd);
+}
+
diff --git a/opcodes/bpf-desc.h b/opcodes/bpf-desc.h
new file mode 100644
index 0000000..5293517
--- /dev/null
+++ b/opcodes/bpf-desc.h
@@ -0,0 +1,266 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* CPU data header for bpf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef BPF_CPU_H
+#define BPF_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CGEN_ARCH bpf
+
+/* Given symbol S, return bpf_cgen_<S>. */
+#define CGEN_SYM(s) bpf##_cgen_##s
+
+
+/* Selected cpu families. */
+#define HAVE_CPU_BPFBF
+
+#define CGEN_INSN_LSB0_P 1
+
+/* Minimum size of any insn (in bytes). */
+#define CGEN_MIN_INSN_SIZE 8
+
+/* Maximum size of any insn (in bytes). */
+#define CGEN_MAX_INSN_SIZE 16
+
+#define CGEN_INT_INSN_P 0
+
+/* Maximum number of syntax elements in an instruction. */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 16
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+ e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
+ we can't hash on everything up to the space. */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction. */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
+
+/* Enums. */
+
+/* Enum declaration for eBPF instruction codes. */
+typedef enum insn_op_code_alu {
+ OP_CODE_ADD = 0, OP_CODE_SUB = 1, OP_CODE_MUL = 2, OP_CODE_DIV = 3
+ , OP_CODE_OR = 4, OP_CODE_AND = 5, OP_CODE_LSH = 6, OP_CODE_RSH = 7
+ , OP_CODE_NEG = 8, OP_CODE_MOD = 9, OP_CODE_XOR = 10, OP_CODE_MOV = 11
+ , OP_CODE_ARSH = 12, OP_CODE_END = 13, OP_CODE_JA = 0, OP_CODE_JEQ = 1
+ , OP_CODE_JGT = 2, OP_CODE_JGE = 3, OP_CODE_JSET = 4, OP_CODE_JNE = 5
+ , OP_CODE_JSGT = 6, OP_CODE_JSGE = 7, OP_CODE_CALL = 8, OP_CODE_EXIT = 9
+ , OP_CODE_JLT = 10, OP_CODE_JLE = 11, OP_CODE_JSLT = 12, OP_CODE_JSLE = 13
+} INSN_OP_CODE_ALU;
+
+/* Enum declaration for eBPF instruction source. */
+typedef enum insn_op_src {
+ OP_SRC_K, OP_SRC_X
+} INSN_OP_SRC;
+
+/* Enum declaration for eBPF instruction class. */
+typedef enum insn_op_class {
+ OP_CLASS_LD = 0, OP_CLASS_LDX = 1, OP_CLASS_ST = 2, OP_CLASS_STX = 3
+ , OP_CLASS_ALU = 4, OP_CLASS_JMP = 5, OP_CLASS_ALU64 = 7
+} INSN_OP_CLASS;
+
+/* Enum declaration for eBPF load/store instruction modes. */
+typedef enum insn_op_mode {
+ OP_MODE_IMM = 0, OP_MODE_ABS = 1, OP_MODE_IND = 2, OP_MODE_MEM = 3
+ , OP_MODE_XADD = 6
+} INSN_OP_MODE;
+
+/* Enum declaration for eBPF load/store instruction sizes. */
+typedef enum insn_op_size {
+ OP_SIZE_W, OP_SIZE_H, OP_SIZE_B, OP_SIZE_DW
+} INSN_OP_SIZE;
+
+/* Attributes. */
+
+/* Enum declaration for machine type selection. */
+typedef enum mach_attr {
+ MACH_BASE, MACH_BPF, MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection. */
+typedef enum isa_attr {
+ ISA_EBPFLE, ISA_EBPFBE, ISA_MAX
+} ISA_ATTR;
+
+/* Number of architecture variants. */
+#define MAX_ISAS ((int) ISA_MAX)
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support. */
+
+/* Ifield attribute indices. */
+
+/* Enum declaration for cgen_ifld attrs. */
+typedef enum cgen_ifld_attr {
+ CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
+ , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr. */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* cgen_ifld attribute accessor macros. */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
+
+/* Enum declaration for bpf ifield types. */
+typedef enum ifield_type {
+ BPF_F_NIL, BPF_F_ANYOF, BPF_F_OP_CODE, BPF_F_OP_SRC
+ , BPF_F_OP_CLASS, BPF_F_OP_MODE, BPF_F_OP_SIZE, BPF_F_DSTLE
+ , BPF_F_SRCLE, BPF_F_DSTBE, BPF_F_SRCBE, BPF_F_REGS
+ , BPF_F_OFFSET16, BPF_F_IMM32, BPF_F_IMM64_A, BPF_F_IMM64_B
+ , BPF_F_IMM64_C, BPF_F_IMM64, BPF_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) BPF_F_MAX)
+
+/* Hardware attribute indices. */
+
+/* Enum declaration for cgen_hw attrs. */
+typedef enum cgen_hw_attr {
+ CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA
+ , CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr. */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* cgen_hw attribute accessor macros. */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
+
+/* Enum declaration for bpf hardware types. */
+typedef enum cgen_hw_type {
+ HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_GPR, HW_H_PC, HW_H_SINT64
+ , HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices. */
+
+/* Enum declaration for cgen_operand attrs. */
+typedef enum cgen_operand_attr {
+ CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
+ , CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr. */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* cgen_operand attribute accessor macros. */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+
+/* Enum declaration for bpf operand types. */
+typedef enum cgen_operand_type {
+ BPF_OPERAND_PC, BPF_OPERAND_DSTLE, BPF_OPERAND_SRCLE, BPF_OPERAND_DSTBE
+ , BPF_OPERAND_SRCBE, BPF_OPERAND_DISP16, BPF_OPERAND_DISP32, BPF_OPERAND_IMM32
+ , BPF_OPERAND_OFFSET16, BPF_OPERAND_IMM64, BPF_OPERAND_ENDSIZE, BPF_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types. */
+#define MAX_OPERANDS 11
+
+/* Maximum number of operands referenced by any insn. */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices. */
+
+/* Enum declaration for cgen_insn attrs. */
+typedef enum cgen_insn_attr {
+ CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
+ , CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr. */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen_insn attribute accessor macros. */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
+
+/* cgen.h uses things we just defined. */
+#include "opcode/cgen.h"
+
+extern const struct cgen_ifld bpf_cgen_ifld_table[];
+
+/* Attributes. */
+extern const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[];
+
+/* Hardware decls. */
+
+extern CGEN_KEYWORD bpf_cgen_opval_h_gpr;
+
+extern const CGEN_HW_ENTRY bpf_cgen_hw_table[];
+
+
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* BPF_CPU_H */
diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c
new file mode 100644
index 0000000..c48bce8
--- /dev/null
+++ b/opcodes/bpf-dis.c
@@ -0,0 +1,624 @@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
+/* Disassembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+ THIS FILE IS MACHINE GENERATED WITH CGEN.
+ - the resultant file is machine generated, cgen-dis.in isn't
+
+ Copyright (C) 1996-2019 Free Software Foundation, Inc.
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "disassemble.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "libiberty.h"
+#include "bpf-desc.h"
+#include "bpf-opc.h"
+#include "opintl.h"
+
+/* Default text to print if an instruction isn't recognized. */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+static void print_normal
+ (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
+static void print_address
+ (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
+static void print_keyword
+ (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
+static void print_insn_normal
+ (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
+static int print_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
+static int default_print_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
+static int read_insn
+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
+ unsigned long *);
+
+/* -- disassembler routines inserted here. */
+
+/* -- dis.c */
+
+/* We need to customize the disassembler a bit:
+ - Use 8 bytes per line by default.
+*/
+
+#define CGEN_PRINT_INSN bpf_print_insn
+
+static int
+bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+ bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ int buflen;
+ int status;
+
+ info->bytes_per_chunk = 1;
+ info->bytes_per_line = 8;
+
+ /* Attempt to read the base part of the insn. */
+ buflen = cd->base_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ /* Try again with the minimum part, if min < base. */
+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+ {
+ buflen = cd->min_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Signed immediates should be printed in hexadecimal. */
+
+static void
+print_immediate (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ int64_t value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ if (value <= 9)
+ (*info->fprintf_func) (info->stream, "%" PRId64, value);
+ else
+ (*info->fprintf_func) (info->stream, "%#" PRIx64, value);
+
+ /* This is to avoid -Wunused-function for print_normal. */
+ if (0)
+ print_normal (cd, dis_info, value, attrs, pc, length);
+}
+
+/* Endianness bit sizes should be printed in decimal. */
+
+static void
+print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ unsigned long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ (*info->fprintf_func) (info->stream, "%lu", value);
+}
+
+
+/* -- */
+
+void bpf_cgen_print_operand
+ (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
+
+/* Main entry point for printing operands.
+ XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
+ of dis-asm.h on cgen.h.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+void
+bpf_cgen_print_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ void * xinfo,
+ CGEN_FIELDS *fields,
+ void const *attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc,
+ int length)
+{
+ disassemble_info *info = (disassemble_info *) xinfo;
+
+ switch (opindex)
+ {
+ case BPF_OPERAND_DISP16 :
+ print_normal (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case BPF_OPERAND_DISP32 :
+ print_normal (cd, info, fields->f_imm32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case BPF_OPERAND_DSTBE :
+ print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstbe, 0);
+ break;
+ case BPF_OPERAND_DSTLE :
+ print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstle, 0);
+ break;
+ case BPF_OPERAND_ENDSIZE :
+ print_endsize (cd, info, fields->f_imm32, 0, pc, length);
+ break;
+ case BPF_OPERAND_IMM32 :
+ print_immediate (cd, info, fields->f_imm32, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case BPF_OPERAND_IMM64 :
+ print_immediate (cd, info, fields->f_imm64, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case BPF_OPERAND_OFFSET16 :
+ print_immediate (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case BPF_OPERAND_SRCBE :
+ print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcbe, 0);
+ break;
+ case BPF_OPERAND_SRCLE :
+ print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcle, 0);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while printing insn"),
+ opindex);
+ abort ();
+ }
+}
+
+cgen_print_fn * const bpf_cgen_print_handlers[] =
+{
+ print_insn_normal,
+};
+
+
+void
+bpf_cgen_init_dis (CGEN_CPU_DESC cd)
+{
+ bpf_cgen_init_opcode_table (cd);
+ bpf_cgen_init_ibld_table (cd);
+ cd->print_handlers = & bpf_cgen_print_handlers[0];
+ cd->print_operand = bpf_cgen_print_operand;
+}
+
+
+/* Default print handler. */
+
+static void
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ long value,
+ unsigned int attrs,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* nothing to do */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", value);
+}
+
+/* Default address handler. */
+
+static void
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ bfd_vma value,
+ unsigned int attrs,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* Nothing to do. */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", (long) value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
+}
+
+/* Keyword print handler. */
+
+static void
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ void *dis_info,
+ CGEN_KEYWORD *keyword_table,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED)
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_KEYWORD_ENTRY *ke;
+
+ ke = cgen_keyword_lookup_value (keyword_table, value);
+ if (ke != NULL)
+ (*info->fprintf_func) (info->stream, "%s", ke->name);
+ else
+ (*info->fprintf_func) (info->stream, "???");
+}
+
+/* Default insn printer.
+
+ DIS_INFO is defined as `void *' so the disassembler needn't know anything
+ about disassemble_info. */
+
+static void
+print_insn_normal (CGEN_CPU_DESC cd,
+ void *dis_info,
+ const CGEN_INSN *insn,
+ CGEN_FIELDS *fields,
+ bfd_vma pc,
+ int length)
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_INIT_PRINT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+ continue;
+ }
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+ continue;
+ }
+
+ /* We have an operand. */
+ bpf_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+ fields, CGEN_INSN_ATTRS (insn), pc, length);
+ }
+}
+
+/* Subroutine of print_insn. Reads an insn into the given buffers and updates
+ the extract info.
+ Returns 0 if all is well, non-zero otherwise. */
+
+static int
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ bfd_vma pc,
+ disassemble_info *info,
+ bfd_byte *buf,
+ int buflen,
+ CGEN_EXTRACT_INFO *ex_info,
+ unsigned long *insn_value)
+{
+ int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ ex_info->dis_info = info;
+ ex_info->valid = (1 << buflen) - 1;
+ ex_info->insn_bytes = buf;
+
+ *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
+ return 0;
+}
+
+/* Utility to print an insn.
+ BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+print_insn (CGEN_CPU_DESC cd,
+ bfd_vma pc,
+ disassemble_info *info,
+ bfd_byte *buf,
+ unsigned int buflen)
+{
+ CGEN_INSN_INT insn_value;
+ const CGEN_INSN_LIST *insn_list;
+ CGEN_EXTRACT_INFO ex_info;
+ int basesize;
+
+ /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
+ basesize = cd->base_insn_bitsize < buflen * 8 ?
+ cd->base_insn_bitsize : buflen * 8;
+ insn_value = cgen_get_insn_value (cd, buf, basesize);
+
+
+ /* Fill in ex_info fields like read_insn would. Don't actually call
+ read_insn, since the incoming buffer is already read (and possibly
+ modified a la m32r). */
+ ex_info.valid = (1 << buflen) - 1;
+ ex_info.dis_info = info;
+ ex_info.insn_bytes = buf;
+
+ /* The instructions are stored in hash lists.
+ Pick the first one and keep trying until we find the right one. */
+
+ insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
+ while (insn_list != NULL)
+ {
+ const CGEN_INSN *insn = insn_list->insn;
+ CGEN_FIELDS fields;
+ int length;
+ unsigned long insn_value_cropped;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! bpf_cgen_insn_supported (cd, insn))
+ {
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ continue;
+ }
+#endif
+
[...]
[diff truncated at 100000 bytes]