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[binutils-gdb] [PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor
- From: Andre Simoes Dias Vieira <avieira at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 16 May 2019 15:39:19 -0000
- Subject: [binutils-gdb] [PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f601a00c4c70f396defc66d592c4786135616545
commit f601a00c4c70f396defc66d592c4786135616545
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date: Wed May 15 17:40:06 2019 +0100
[PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operands.
(parse_operands): Handle new operands.
(enum vfp_or_neon_is_neon_bits): Moved
(vfp_or_neon_is_neon): Moved
(check_simd_pred_availability): Moved.
(do_neon_logic): Change to accept MVE variants.
(insns): Changed to accept MVE variants.
* testsuite/gas/arm/mve-vand-bad.d: New test.
* testsuite/gas/arm/mve-vand-bad.l: New test.
* testsuite/gas/arm/mve-vand-bad.s: New test.
* testsuite/gas/arm/mve-vbic-bad.d: New test.
* testsuite/gas/arm/mve-vbic-bad.l: New test.
* testsuite/gas/arm/mve-vbic-bad.s: New test.
* testsuite/gas/arm/mve-veor-bad.d: New test.
* testsuite/gas/arm/mve-veor-bad.l: New test.
* testsuite/gas/arm/mve-veor-bad.s: New test.
* testsuite/gas/arm/mve-vorn-bad.d: New test.
* testsuite/gas/arm/mve-vorn-bad.l: New test.
* testsuite/gas/arm/mve-vorn-bad.s: New test.
* testsuite/gas/arm/mve-vorr-bad.d: New test.
* testsuite/gas/arm/mve-vorr-bad.l: New test.
* testsuite/gas/arm/mve-vorr-bad.s: New test.
Diff:
---
gas/ChangeLog | 25 ++++
gas/config/tc-arm.c | 217 ++++++++++++++++++++---------------
gas/testsuite/gas/arm/mve-vand-bad.d | 5 +
gas/testsuite/gas/arm/mve-vand-bad.l | 27 +++++
gas/testsuite/gas/arm/mve-vand-bad.s | 38 ++++++
gas/testsuite/gas/arm/mve-vbic-bad.d | 5 +
gas/testsuite/gas/arm/mve-vbic-bad.l | 28 +++++
gas/testsuite/gas/arm/mve-vbic-bad.s | 38 ++++++
gas/testsuite/gas/arm/mve-veor-bad.d | 5 +
gas/testsuite/gas/arm/mve-veor-bad.l | 12 ++
gas/testsuite/gas/arm/mve-veor-bad.s | 18 +++
gas/testsuite/gas/arm/mve-vorn-bad.d | 5 +
gas/testsuite/gas/arm/mve-vorn-bad.l | 27 +++++
gas/testsuite/gas/arm/mve-vorn-bad.s | 38 ++++++
gas/testsuite/gas/arm/mve-vorr-bad.d | 5 +
gas/testsuite/gas/arm/mve-vorr-bad.l | 27 +++++
gas/testsuite/gas/arm/mve-vorr-bad.s | 38 ++++++
17 files changed, 464 insertions(+), 94 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 74a3173..cb11107 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,30 @@
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ * config/tc-arm.c (enum operand_parse_code): New operands.
+ (parse_operands): Handle new operands.
+ (enum vfp_or_neon_is_neon_bits): Moved
+ (vfp_or_neon_is_neon): Moved
+ (check_simd_pred_availability): Moved.
+ (do_neon_logic): Change to accept MVE variants.
+ (insns): Changed to accept MVE variants.
+ * testsuite/gas/arm/mve-vand-bad.d: New test.
+ * testsuite/gas/arm/mve-vand-bad.l: New test.
+ * testsuite/gas/arm/mve-vand-bad.s: New test.
+ * testsuite/gas/arm/mve-vbic-bad.d: New test.
+ * testsuite/gas/arm/mve-vbic-bad.l: New test.
+ * testsuite/gas/arm/mve-vbic-bad.s: New test.
+ * testsuite/gas/arm/mve-veor-bad.d: New test.
+ * testsuite/gas/arm/mve-veor-bad.l: New test.
+ * testsuite/gas/arm/mve-veor-bad.s: New test.
+ * testsuite/gas/arm/mve-vorn-bad.d: New test.
+ * testsuite/gas/arm/mve-vorn-bad.l: New test.
+ * testsuite/gas/arm/mve-vorn-bad.s: New test.
+ * testsuite/gas/arm/mve-vorr-bad.d: New test.
+ * testsuite/gas/arm/mve-vorr-bad.l: New test.
+ * testsuite/gas/arm/mve-vorr-bad.s: New test.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
* config/tc-arm.c (M_MNEM_vaddlv, M_MNEM_vaddlva, M_MNEM_vaddv,
M_MNEM_vaddva): New instruction encodings.
(mve_encode_rq): New encoding helper function.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 192de0b..9510d7d 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -6954,6 +6954,8 @@ enum operand_parse_code
OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
OP_VMOV, /* Neon VMOV operands. */
OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
+ /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
+ OP_RNDQMQ_Ibig,
OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
OP_VLDR, /* VLDR operand. */
@@ -7368,6 +7370,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
break;
+ case OP_RNDQMQ_Ibig:
+ po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig);
+ break;
+ try_rndq_ibig:
case OP_RNDQ_Ibig:
{
po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
@@ -16002,12 +16008,104 @@ neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
return FAIL;
}
+enum vfp_or_neon_is_neon_bits
+{
+NEON_CHECK_CC = 1,
+NEON_CHECK_ARCH = 2,
+NEON_CHECK_ARCH8 = 4
+};
+
+/* Call this function if an instruction which may have belonged to the VFP or
+ Neon instruction sets, but turned out to be a Neon instruction (due to the
+ operand types involved, etc.). We have to check and/or fix-up a couple of
+ things:
+
+ - Make sure the user hasn't attempted to make a Neon instruction
+ conditional.
+ - Alter the value in the condition code field if necessary.
+ - Make sure that the arch supports Neon instructions.
+
+ Which of these operations take place depends on bits from enum
+ vfp_or_neon_is_neon_bits.
+
+ WARNING: This function has side effects! If NEON_CHECK_CC is used and the
+ current instruction's condition is COND_ALWAYS, the condition field is
+ changed to inst.uncond_value. This is necessary because instructions shared
+ between VFP and Neon may be conditional for the VFP variants only, and the
+ unconditional Neon version must have, e.g., 0xF in the condition field. */
+
+static int
+vfp_or_neon_is_neon (unsigned check)
+{
+/* Conditions are always legal in Thumb mode (IT blocks). */
+if (!thumb_mode && (check & NEON_CHECK_CC))
+ {
+ if (inst.cond != COND_ALWAYS)
+ {
+ first_error (_(BAD_COND));
+ return FAIL;
+ }
+ if (inst.uncond_value != -1)
+ inst.instruction |= inst.uncond_value << 28;
+ }
+
+
+ if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
+ || ((check & NEON_CHECK_ARCH8)
+ && !mark_feature_used (&fpu_neon_ext_armv8)))
+ {
+ first_error (_(BAD_FPU));
+ return FAIL;
+ }
+
+return SUCCESS;
+}
+
+static int
+check_simd_pred_availability (int fp, unsigned check)
+{
+if (inst.cond > COND_ALWAYS)
+ {
+ if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+ {
+ inst.error = BAD_FPU;
+ return 1;
+ }
+ inst.pred_insn_type = INSIDE_VPT_INSN;
+ }
+else if (inst.cond < COND_ALWAYS)
+ {
+ if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+ else if (vfp_or_neon_is_neon (check) == FAIL)
+ return 2;
+ }
+else
+ {
+ if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
+ && vfp_or_neon_is_neon (check) == FAIL)
+ return 3;
+
+ if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+ }
+return 0;
+}
+
static void
do_neon_logic (void)
{
if (inst.operands[2].present && inst.operands[2].isreg)
{
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+ if (rs == NS_QQQ
+ && check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)
+ == FAIL)
+ return;
+ else if (rs != NS_QQQ
+ && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
+ first_error (BAD_FPU);
+
neon_check_type (3, rs, N_IGNORE_TYPE);
/* U bit and size field were set as part of the bitmask. */
NEON_ENCODE (INTEGER, inst);
@@ -16021,14 +16119,29 @@ do_neon_logic (void)
enum neon_shape rs = (three_ops_form
? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
: neon_select_shape (NS_DI, NS_QI, NS_NULL));
- struct neon_type_el et = neon_check_type (2, rs,
- N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
+ /* Because neon_select_shape makes the second operand a copy of the first
+ if the second operand is not present. */
+ if (rs == NS_QQI
+ && check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)
+ == FAIL)
+ return;
+ else if (rs != NS_QQI
+ && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
+ first_error (BAD_FPU);
+
+ struct neon_type_el et;
+ if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+ et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK);
+ else
+ et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32
+ | N_KEY, N_EQK);
+
+ if (et.type == NT_invtype)
+ return;
enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
unsigned immbits;
int cmode;
- if (et.type == NT_invtype)
- return;
if (three_ops_form)
constraint (inst.operands[0].reg != inst.operands[1].reg,
@@ -16138,90 +16251,6 @@ do_neon_dyadic_if_i_d (void)
neon_dyadic_misc (NT_untyped, N_IF_32, 0);
}
-enum vfp_or_neon_is_neon_bits
-{
- NEON_CHECK_CC = 1,
- NEON_CHECK_ARCH = 2,
- NEON_CHECK_ARCH8 = 4
-};
-
-/* Call this function if an instruction which may have belonged to the VFP or
- Neon instruction sets, but turned out to be a Neon instruction (due to the
- operand types involved, etc.). We have to check and/or fix-up a couple of
- things:
-
- - Make sure the user hasn't attempted to make a Neon instruction
- conditional.
- - Alter the value in the condition code field if necessary.
- - Make sure that the arch supports Neon instructions.
-
- Which of these operations take place depends on bits from enum
- vfp_or_neon_is_neon_bits.
-
- WARNING: This function has side effects! If NEON_CHECK_CC is used and the
- current instruction's condition is COND_ALWAYS, the condition field is
- changed to inst.uncond_value. This is necessary because instructions shared
- between VFP and Neon may be conditional for the VFP variants only, and the
- unconditional Neon version must have, e.g., 0xF in the condition field. */
-
-static int
-vfp_or_neon_is_neon (unsigned check)
-{
- /* Conditions are always legal in Thumb mode (IT blocks). */
- if (!thumb_mode && (check & NEON_CHECK_CC))
- {
- if (inst.cond != COND_ALWAYS)
- {
- first_error (_(BAD_COND));
- return FAIL;
- }
- if (inst.uncond_value != -1)
- inst.instruction |= inst.uncond_value << 28;
- }
-
-
- if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
- || ((check & NEON_CHECK_ARCH8)
- && !mark_feature_used (&fpu_neon_ext_armv8)))
- {
- first_error (_(BAD_FPU));
- return FAIL;
- }
-
- return SUCCESS;
-}
-
-static int
-check_simd_pred_availability (int fp, unsigned check)
-{
- if (inst.cond > COND_ALWAYS)
- {
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
- {
- inst.error = BAD_FPU;
- return 1;
- }
- inst.pred_insn_type = INSIDE_VPT_INSN;
- }
- else if (inst.cond < COND_ALWAYS)
- {
- if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
- inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
- else if (vfp_or_neon_is_neon (check) == FAIL)
- return 2;
- }
- else
- {
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
- && vfp_or_neon_is_neon (check) == FAIL)
- return 3;
-
- if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
- inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
- }
- return 0;
-}
-
static void
do_mve_vstr_vldr_QI (int size, int elsize, int load)
{
@@ -23347,15 +23376,10 @@ static const struct asm_opcode insns[] =
nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
/* Logic ops, types optional & ignored. */
- nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
- nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
- nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
- nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
- nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
/* Bitfield ops, untyped. */
NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
@@ -24108,10 +24132,15 @@ static const struct asm_opcode insns[] =
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_neon_ext_v1
- mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
+ mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
+ mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
+ mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
+ mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
+ mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
+ mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
diff --git a/gas/testsuite/gas/arm/mve-vand-bad.d b/gas/testsuite/gas/arm/mve-vand-bad.d
new file mode 100644
index 0000000..1889759
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vand-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VAND instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vand-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vand-bad.l b/gas/testsuite/gas/arm/mve-vand-bad.l
new file mode 100644
index 0000000..f6044b1
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vand-bad.l
@@ -0,0 +1,27 @@
+[^:]*: Assembler messages:
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vandeq q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vandeq q0,q1,q2'
+[^:]*:22: Error: syntax error -- `vandeq q0,q1,q2'
+[^:]*:24: Error: instruction missing MVE vector predication code -- `vand q0,q1,q2'
+[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vandt q0,q1,q2'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Error: syntax error -- `vandeq.i16 q0,#255'
+[^:]*:29: Error: syntax error -- `vandeq.i16 q0,#255'
+[^:]*:31: Error: syntax error -- `vandeq.i16 q0,#255'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vand.i16 q0,#255'
+[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vandt.i16 q0,#255'
+[^:]*:35: Error: bad type in SIMD instruction -- `vand.i8 q0,#255'
+[^:]*:36: Error: bad type in SIMD instruction -- `vand.i64 q0,#255'
+[^:]*:37: Error: immediate value out of range -- `vand.i16 q0,#0'
+[^:]*:38: Error: immediate value out of range -- `vand.i32 q0,#0'
diff --git a/gas/testsuite/gas/arm/mve-vand-bad.s b/gas/testsuite/gas/arm/mve-vand-bad.s
new file mode 100644
index 0000000..77f27bd
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vand-bad.s
@@ -0,0 +1,38 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vand q0, q1, q2
+.endr
+.endm
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vand.i16 q0, #255
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond1
+it eq
+vandeq q0, q1, q2
+vandeq q0, q1, q2
+vpst
+vandeq q0, q1, q2
+vpst
+vand q0, q1, q2
+vandt q0, q1, q2
+cond2
+it eq
+vandeq.i16 q0, #255
+vandeq.i16 q0, #255
+vpst
+vandeq.i16 q0, #255
+vpst
+vand.i16 q0, #255
+vandt.i16 q0, #255
+vand.i8 q0, #255
+vand.i64 q0, #255
+vand.i16 q0, #0
+vand.i32 q0, #0
diff --git a/gas/testsuite/gas/arm/mve-vbic-bad.d b/gas/testsuite/gas/arm/mve-vbic-bad.d
new file mode 100644
index 0000000..5c17bf4
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vbic-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VBIC instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vbic-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vbic-bad.l b/gas/testsuite/gas/arm/mve-vbic-bad.l
new file mode 100644
index 0000000..10deb9d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vbic-bad.l
@@ -0,0 +1,28 @@
+[^:]*: Assembler messages:
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vbiceq q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vbiceq q0,q1,q2'
+[^:]*:22: Error: syntax error -- `vbiceq q0,q1,q2'
+[^:]*:24: Error: instruction missing MVE vector predication code -- `vbic q0,q1,q2'
+[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vbict q0,q1,q2'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Error: syntax error -- `vbiceq.i16 q0,#255'
+[^:]*:29: Error: syntax error -- `vbiceq.i16 q0,#255'
+[^:]*:31: Error: syntax error -- `vbiceq.i16 q0,#255'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vbic.i16 q0,#255'
+[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vbict.i16 q0,#255'
+[^:]*:35: Error: bad type in SIMD instruction -- `vbic.i8 q0,#255'
+[^:]*:36: Error: bad type in SIMD instruction -- `vbic.i64 q0,#255'
+[^:]*:37: Error: immediate value out of range -- `vbic.i16 q0,#257'
+[^:]*:38: Error: immediate value out of range -- `vbic.i32 q0,#257'
+
diff --git a/gas/testsuite/gas/arm/mve-vbic-bad.s b/gas/testsuite/gas/arm/mve-vbic-bad.s
new file mode 100644
index 0000000..4f35158
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vbic-bad.s
@@ -0,0 +1,38 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vbic q0, q1, q2
+.endr
+.endm
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vbic.i16 q0, #255
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond1
+it eq
+vbiceq q0, q1, q2
+vbiceq q0, q1, q2
+vpst
+vbiceq q0, q1, q2
+vpst
+vbic q0, q1, q2
+vbict q0, q1, q2
+cond2
+it eq
+vbiceq.i16 q0, #255
+vbiceq.i16 q0, #255
+vpst
+vbiceq.i16 q0, #255
+vpst
+vbic.i16 q0, #255
+vbict.i16 q0, #255
+vbic.i8 q0, #255
+vbic.i64 q0, #255
+vbic.i16 q0, #257
+vbic.i32 q0, #257
diff --git a/gas/testsuite/gas/arm/mve-veor-bad.d b/gas/testsuite/gas/arm/mve-veor-bad.d
new file mode 100644
index 0000000..e512286
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-veor-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VEOR instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-veor-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-veor-bad.l b/gas/testsuite/gas/arm/mve-veor-bad.l
new file mode 100644
index 0000000..3da9c71
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-veor-bad.l
@@ -0,0 +1,12 @@
+[^:]*: Assembler messages:
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Error: syntax error -- `veoreq q0,q1,q2'
+[^:]*:13: Error: syntax error -- `veoreq q0,q1,q2'
+[^:]*:15: Error: syntax error -- `veoreq q0,q1,q2'
+[^:]*:17: Error: instruction missing MVE vector predication code -- `veor q0,q1,q2'
+[^:]*:18: Error: vector predicated instruction should be in VPT/VPST block -- `veort q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-veor-bad.s b/gas/testsuite/gas/arm/mve-veor-bad.s
new file mode 100644
index 0000000..ffc1a00
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-veor-bad.s
@@ -0,0 +1,18 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+veor q0, q1, q2
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond
+it eq
+veoreq q0, q1, q2
+veoreq q0, q1, q2
+vpst
+veoreq q0, q1, q2
+vpst
+veor q0, q1, q2
+veort q0, q1, q2
diff --git a/gas/testsuite/gas/arm/mve-vorn-bad.d b/gas/testsuite/gas/arm/mve-vorn-bad.d
new file mode 100644
index 0000000..e78957f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorn-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VORN instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vorn-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vorn-bad.l b/gas/testsuite/gas/arm/mve-vorn-bad.l
new file mode 100644
index 0000000..69e479b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorn-bad.l
@@ -0,0 +1,27 @@
+[^:]*: Assembler messages:
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vorneq q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vorneq q0,q1,q2'
+[^:]*:22: Error: syntax error -- `vorneq q0,q1,q2'
+[^:]*:24: Error: instruction missing MVE vector predication code -- `vorn q0,q1,q2'
+[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vornt q0,q1,q2'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Error: syntax error -- `vorneq.i16 q0,#255'
+[^:]*:29: Error: syntax error -- `vorneq.i16 q0,#255'
+[^:]*:31: Error: syntax error -- `vorneq.i16 q0,#255'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vorn.i16 q0,#255'
+[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vornt.i16 q0,#255'
+[^:]*:35: Error: bad type in SIMD instruction -- `vorn.i8 q0,#255'
+[^:]*:36: Error: bad type in SIMD instruction -- `vorn.i64 q0,#255'
+[^:]*:37: Error: immediate value out of range -- `vorn.i16 q0,#0'
+[^:]*:38: Error: immediate value out of range -- `vorn.i32 q0,#0'
diff --git a/gas/testsuite/gas/arm/mve-vorn-bad.s b/gas/testsuite/gas/arm/mve-vorn-bad.s
new file mode 100644
index 0000000..9a2edb0
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorn-bad.s
@@ -0,0 +1,38 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vorn q0, q1, q2
+.endr
+.endm
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vorn.i16 q0, #255
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond1
+it eq
+vorneq q0, q1, q2
+vorneq q0, q1, q2
+vpst
+vorneq q0, q1, q2
+vpst
+vorn q0, q1, q2
+vornt q0, q1, q2
+cond2
+it eq
+vorneq.i16 q0, #255
+vorneq.i16 q0, #255
+vpst
+vorneq.i16 q0, #255
+vpst
+vorn.i16 q0, #255
+vornt.i16 q0, #255
+vorn.i8 q0, #255
+vorn.i64 q0, #255
+vorn.i16 q0, #0
+vorn.i32 q0, #0
diff --git a/gas/testsuite/gas/arm/mve-vorr-bad.d b/gas/testsuite/gas/arm/mve-vorr-bad.d
new file mode 100644
index 0000000..4e94b8a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorr-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VORR instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vorr-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vorr-bad.l b/gas/testsuite/gas/arm/mve-vorr-bad.l
new file mode 100644
index 0000000..19a0ab8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorr-bad.l
@@ -0,0 +1,27 @@
+[^:]*: Assembler messages:
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vorreq q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vorreq q0,q1,q2'
+[^:]*:22: Error: syntax error -- `vorreq q0,q1,q2'
+[^:]*:24: Error: instruction missing MVE vector predication code -- `vorr q0,q1,q2'
+[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vorrt q0,q1,q2'
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Error: syntax error -- `vorreq.i16 q0,#255'
+[^:]*:29: Error: syntax error -- `vorreq.i16 q0,#255'
+[^:]*:31: Error: syntax error -- `vorreq.i16 q0,#255'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vorr.i16 q0,#255'
+[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vorrt.i16 q0,#255'
+[^:]*:35: Error: bad type in SIMD instruction -- `vorr.i8 q0,#255'
+[^:]*:36: Error: bad type in SIMD instruction -- `vorr.i64 q0,#255'
+[^:]*:37: Error: immediate value out of range -- `vorr.i16 q0,#257'
+[^:]*:38: Error: immediate value out of range -- `vorr.i32 q0,#257'
diff --git a/gas/testsuite/gas/arm/mve-vorr-bad.s b/gas/testsuite/gas/arm/mve-vorr-bad.s
new file mode 100644
index 0000000..671e35f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vorr-bad.s
@@ -0,0 +1,38 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vorr q0, q1, q2
+.endr
+.endm
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vorr.i16 q0, #255
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond1
+it eq
+vorreq q0, q1, q2
+vorreq q0, q1, q2
+vpst
+vorreq q0, q1, q2
+vpst
+vorr q0, q1, q2
+vorrt q0, q1, q2
+cond2
+it eq
+vorreq.i16 q0, #255
+vorreq.i16 q0, #255
+vpst
+vorreq.i16 q0, #255
+vpst
+vorr.i16 q0, #255
+vorrt.i16 q0, #255
+vorr.i8 q0, #255
+vorr.i64 q0, #255
+vorr.i16 q0, #257
+vorr.i32 q0, #257