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[binutils-gdb] [binutils][aarch64] Introduce SVE_IMM_ROT3 operand.
- From: Matthew Malcomson <matmal01 at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 9 May 2019 09:30:54 -0000
- Subject: [binutils-gdb] [binutils][aarch64] Introduce SVE_IMM_ROT3 operand.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=adccc50753467ac66573471f180a60d8d96ce223
commit adccc50753467ac66573471f180a60d8d96ce223
Author: Matthew Malcomson <matthew.malcomson@arm.com>
Date: Thu May 9 10:29:15 2019 +0100
[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate
operand encoded at bit position 10.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_IMM_ROT3.
(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
(fields): Handle SVE_rot3 field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
Diff:
---
gas/ChangeLog | 4 ++++
gas/config/tc-aarch64.c | 1 +
include/ChangeLog | 4 ++++
include/opcode/aarch64.h | 1 +
opcodes/ChangeLog | 12 ++++++++++++
opcodes/aarch64-asm-2.c | 39 ++++++++++++++++++++-------------------
opcodes/aarch64-dis-2.c | 39 ++++++++++++++++++++-------------------
opcodes/aarch64-opc-2.c | 1 +
opcodes/aarch64-opc.c | 3 +++
opcodes/aarch64-opc.h | 1 +
opcodes/aarch64-tbl.h | 2 ++
11 files changed, 69 insertions(+), 38 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c21493f..ff3e49b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,9 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index b07a722..9f3a958 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5782,6 +5782,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_IMM_ROT3:
case AARCH64_OPND_SVE_IMM_ROT1:
case AARCH64_OPND_SVE_IMM_ROT2:
+ case AARCH64_OPND_SVE_IMM_ROT3:
po_imm_nc_or_fail ();
info->imm.value = val;
break;
diff --git a/include/ChangeLog b/include/ChangeLog
index 1ce57a4..14415ed 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,9 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index fdc7cde..e392499 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -372,6 +372,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
+ AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e09c02e..a1a842d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,17 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+ * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+ for SVE_IMM_ROT3.
+ (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
+ (fields): Handle SVE_rot3 field.
+ * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
+ * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
* aarch64-opc.c (verify_constraints): Check for movprfx for sve2
instructions.
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index c7f8e8b..dbfb431 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -628,7 +628,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 28:
case 29:
case 30:
- case 160:
case 161:
case 162:
case 163:
@@ -638,7 +637,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 167:
case 168:
case 169:
- case 182:
+ case 170:
case 183:
case 184:
case 185:
@@ -647,8 +646,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 188:
case 189:
case 190:
- case 194:
- case 197:
+ case 191:
+ case 195:
+ case 198:
return aarch64_ins_regno (self, info, code, inst, errors);
case 14:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
- case 200:
+ case 201:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 35:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -694,9 +694,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 80:
case 81:
case 82:
- case 157:
- case 159:
- case 174:
+ case 158:
+ case 160:
case 175:
case 176:
case 177:
@@ -704,7 +703,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 179:
case 180:
case 181:
- case 199:
+ case 182:
+ case 200:
return aarch64_ins_imm (self, info, code, inst, errors);
case 43:
case 44:
@@ -717,7 +717,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 148:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 68:
- case 155:
+ case 156:
return aarch64_ins_limm (self, info, code, inst, errors);
case 69:
return aarch64_ins_aimm (self, info, code, inst, errors);
@@ -731,6 +731,7 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 75:
case 152:
+ case 154:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 76:
case 77:
@@ -832,26 +833,26 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 151:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 154:
+ case 155:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 156:
+ case 157:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 158:
+ case 159:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 170:
case 171:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 172:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 173:
+ case 174:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 191:
case 192:
case 193:
+ case 194:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 195:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 196:
- case 198:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 197:
+ case 199:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index ee7dabc..dc37212 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -20059,7 +20059,6 @@ aarch64_extract_operand (const aarch64_operand *self,
case 28:
case 29:
case 30:
- case 160:
case 161:
case 162:
case 163:
@@ -20069,7 +20068,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 167:
case 168:
case 169:
- case 182:
+ case 170:
case 183:
case 184:
case 185:
@@ -20078,8 +20077,9 @@ aarch64_extract_operand (const aarch64_operand *self,
case 188:
case 189:
case 190:
- case 194:
- case 197:
+ case 191:
+ case 195:
+ case 198:
return aarch64_ext_regno (self, info, code, inst, errors);
case 9:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -20095,7 +20095,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
- case 200:
+ case 201:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 35:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -20130,9 +20130,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 80:
case 81:
case 82:
- case 157:
- case 159:
- case 174:
+ case 158:
+ case 160:
case 175:
case 176:
case 177:
@@ -20140,7 +20139,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 179:
case 180:
case 181:
- case 199:
+ case 182:
+ case 200:
return aarch64_ext_imm (self, info, code, inst, errors);
case 43:
case 44:
@@ -20155,7 +20155,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 148:
return aarch64_ext_fpimm (self, info, code, inst, errors);
case 68:
- case 155:
+ case 156:
return aarch64_ext_limm (self, info, code, inst, errors);
case 69:
return aarch64_ext_aimm (self, info, code, inst, errors);
@@ -20169,6 +20169,7 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
case 75:
case 152:
+ case 154:
return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
case 76:
case 77:
@@ -20270,26 +20271,26 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
case 151:
return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
- case 154:
+ case 155:
return aarch64_ext_inv_limm (self, info, code, inst, errors);
- case 156:
+ case 157:
return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
- case 158:
+ case 159:
return aarch64_ext_sve_scale (self, info, code, inst, errors);
- case 170:
case 171:
- return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 172:
+ return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 173:
+ case 174:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
- case 191:
case 192:
case 193:
+ case 194:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
- case 195:
- return aarch64_ext_sve_index (self, info, code, inst, errors);
case 196:
- case 198:
+ return aarch64_ext_sve_index (self, info, code, inst, errors);
+ case 197:
+ case 199:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 96eedd7..9f9e000 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -178,6 +178,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot1}, "a 1-bit rotation specifier for complex arithmetic operations"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot2}, "a 2-bit rotation specifier for complex arithmetic operations"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot3}, "a 1-bit rotation specifier for complex arithmetic operations"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a3f38a9..eb3a1e4 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -309,6 +309,7 @@ const aarch64_field fields[] =
{ 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
{ 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
{ 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
+ { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
{ 22, 1 }, /* SVE_sz: 1-bit element size select. */
{ 16, 4 }, /* SVE_tsz: triangular size select. */
{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
@@ -2231,6 +2232,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_IMM_ROT3:
case AARCH64_OPND_SVE_IMM_ROT1:
+ case AARCH64_OPND_SVE_IMM_ROT3:
if (opnd->imm.value != 90 && opnd->imm.value != 270)
{
set_other_error (mismatch_detail, idx,
@@ -3346,6 +3348,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_IMM_ROT3:
case AARCH64_OPND_SVE_IMM_ROT1:
case AARCH64_OPND_SVE_IMM_ROT2:
+ case AARCH64_OPND_SVE_IMM_ROT3:
snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
break;
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index f6c506d..b1060d4 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -136,6 +136,7 @@ enum aarch64_field_kind
FLD_SVE_prfop,
FLD_SVE_rot1,
FLD_SVE_rot2,
+ FLD_SVE_rot3,
FLD_SVE_sz,
FLD_SVE_tsz,
FLD_SVE_tszh,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 481caea..6be57f0 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4879,6 +4879,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
"a 1-bit rotation specifier for complex arithmetic operations") \
Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD_SVE_rot2), \
"a 2-bit rotation specifier for complex arithmetic operations") \
+ Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT3", 0, F(FLD_SVE_rot3), \
+ "a 1-bit rotation specifier for complex arithmetic operations") \
Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \
F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \
"an inverted 13-bit logical immediate") \