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[binutils-gdb] x86: Support Intel AVX512 BF16
- From: H.J.Lu <hjl at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 5 Apr 2019 18:04:13 -0000
- Subject: [binutils-gdb] x86: Support Intel AVX512 BF16
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=d6aab7a11b8bd85de43f9fe6b1cea95b504e73ad
commit d6aab7a11b8bd85de43f9fe6b1cea95b504e73ad
Author: Xuepeng Guo <xuepeng.guo@intel.com>
Date: Fri Apr 5 11:03:01 2019 -0700
x86: Support Intel AVX512 BF16
Add assembler and disassembler support Intel AVX512 BF16:
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
gas/
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_bf16.
(cpu_noarch): Add noavx512_bf16.
* doc/c-i386.texi: Document avx512_bf16.
* testsuite/gas/i386/avx512_bf16.d: New file.
* testsuite/gas/i386/avx512_bf16.s: Likewise.
* testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
* testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
* testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
* testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
* testsuite/gas/i386/i386.exp: Add BF16 related tests.
opcodes/
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
* i386-dis-evex.h (evex_table): Updated to support BF16
instructions.
* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
and EVEX_W_0F3872_P_3.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
(cpu_flags): Add bitfield for CpuAVX512_BF16.
* i386-opc.h (enum): Add CpuAVX512_BF16.
(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
* i386-opc.tbl: Add AVX512 BF16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Diff:
---
gas/ChangeLog | 19 +
gas/config/tc-i386.c | 3 +
gas/doc/c-i386.texi | 4 +-
gas/testsuite/gas/i386/avx512_bf16.d | 42 +
gas/testsuite/gas/i386/avx512_bf16.s | 37 +
gas/testsuite/gas/i386/avx512_bf16_vl-inval.l | 7 +
gas/testsuite/gas/i386/avx512_bf16_vl-inval.s | 13 +
gas/testsuite/gas/i386/avx512_bf16_vl.d | 70 +
gas/testsuite/gas/i386/avx512_bf16_vl.s | 65 +
gas/testsuite/gas/i386/i386.exp | 6 +
gas/testsuite/gas/i386/x86-64-avx512_bf16.d | 42 +
gas/testsuite/gas/i386/x86-64-avx512_bf16.s | 37 +
.../gas/i386/x86-64-avx512_bf16_vl-inval.l | 7 +
.../gas/i386/x86-64-avx512_bf16_vl-inval.s | 13 +
gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.d | 70 +
gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.s | 65 +
opcodes/ChangeLog | 14 +
opcodes/i386-dis-evex.h | 20 +-
opcodes/i386-dis.c | 3 +
opcodes/i386-gen.c | 7 +-
opcodes/i386-init.h | 378 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 30 +
opcodes/i386-tbl.h | 8254 ++++++++++----------
24 files changed, 5075 insertions(+), 4134 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 669dd39..27d3604 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,22 @@
+2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add .avx512_bf16.
+ (cpu_noarch): Add noavx512_bf16.
+ * doc/c-i386.texi: Document avx512_bf16.
+ * testsuite/gas/i386/avx512_bf16.d: New file.
+ * testsuite/gas/i386/avx512_bf16.s: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Add BF16 related tests.
+
2019-04-05 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/bc.s,
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 690fd23..ed8cfe1 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1080,6 +1080,8 @@ static const arch_entry cpu_arch[] =
CPU_MOVDIRI_FLAGS, 0 },
{ STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
CPU_MOVDIR64B_FLAGS, 0 },
+ { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN,
+ CPU_AVX512_BF16_FLAGS, 0 },
};
static const noarch_entry cpu_noarch[] =
@@ -1119,6 +1121,7 @@ static const noarch_entry cpu_noarch[] =
{ STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
{ STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
{ STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
+ { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS },
};
#ifdef I386COFF
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 4acd5ff..86cde79 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -198,6 +198,7 @@ accept various extension mnemonics. For example,
@code{avx512_vbmi2},
@code{avx512_vnni},
@code{avx512_bitalg},
+@code{avx512_bf16},
@code{noavx512f},
@code{noavx512cd},
@code{noavx512er},
@@ -213,6 +214,7 @@ accept various extension mnemonics. For example,
@code{noavx512_vbmi2},
@code{noavx512_vnni},
@code{noavx512_bitalg},
+@code{noavx512_bf16},
@code{vmx},
@code{vmfunc},
@code{smx},
@@ -1303,7 +1305,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
-@item @samp{.avx512_bitalg}
+@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
diff --git a/gas/testsuite/gas/i386/avx512_bf16.d b/gas/testsuite/gas/i386/avx512_bf16.d
new file mode 100644
index 0000000..e988ce8
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_bf16.d
@@ -0,0 +1,42 @@
+#as:
+#objdump: -dw
+#name: i386 BF16 insns
+#source: avx512_bf16.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 62 f2 57 48 72 f4 vcvtne2ps2bf16 %zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 57 4f 72 b4 f4 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%esp,%esi,8\),%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 57 58 72 31 vcvtne2ps2bf16 \(%ecx\)\{1to16\},%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 57 48 72 71 7f vcvtne2ps2bf16 0x1fc0\(%ecx\),%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 57 df 72 b2 00 e0 ff ff vcvtne2ps2bf16 -0x2000\(%edx\)\{1to16\},%zmm5,%zmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 7e 48 72 f5 vcvtneps2bf16 %zmm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 7e 4f 72 b4 f4 00 00 00 10 vcvtneps2bf16 0x10000000\(%esp,%esi,8\),%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 7e 58 72 31 vcvtneps2bf16 \(%ecx\)\{1to16\},%ymm6
+[ ]*[a-f0-9]+: 62 f2 7e 48 72 71 7f vcvtneps2bf16 0x1fc0\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: 62 f2 7e df 72 b2 00 e0 ff ff vcvtneps2bf16 -0x2000\(%edx\)\{1to16\},%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 56 48 52 f4 vdpbf16ps %zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 56 4f 52 b4 f4 00 00 00 10 vdpbf16ps 0x10000000\(%esp,%esi,8\),%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 56 58 52 31 vdpbf16ps \(%ecx\)\{1to16\},%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 56 48 52 71 7f vdpbf16ps 0x1fc0\(%ecx\),%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 56 df 52 b2 00 e0 ff ff vdpbf16ps -0x2000\(%edx\)\{1to16\},%zmm5,%zmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 57 48 72 f4 vcvtne2ps2bf16 %zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 57 4f 72 b4 f4 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%esp,%esi,8\),%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 57 58 72 31 vcvtne2ps2bf16 \(%ecx\)\{1to16\},%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 57 48 72 71 7f vcvtne2ps2bf16 0x1fc0\(%ecx\),%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 57 df 72 b2 00 e0 ff ff vcvtne2ps2bf16 -0x2000\(%edx\)\{1to16\},%zmm5,%zmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 7e 48 72 f5 vcvtneps2bf16 %zmm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 7e 4f 72 b4 f4 00 00 00 10 vcvtneps2bf16 0x10000000\(%esp,%esi,8\),%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 7e 58 72 31 vcvtneps2bf16 \(%ecx\)\{1to16\},%ymm6
+[ ]*[a-f0-9]+: 62 f2 7e 48 72 71 7f vcvtneps2bf16 0x1fc0\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: 62 f2 7e df 72 b2 00 e0 ff ff vcvtneps2bf16 -0x2000\(%edx\)\{1to16\},%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 56 48 52 f4 vdpbf16ps %zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 56 4f 52 b4 f4 00 00 00 10 vdpbf16ps 0x10000000\(%esp,%esi,8\),%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 56 58 52 31 vdpbf16ps \(%ecx\)\{1to16\},%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 56 48 52 71 7f vdpbf16ps 0x1fc0\(%ecx\),%zmm5,%zmm6
+[ ]*[a-f0-9]+: 62 f2 56 df 52 b2 00 e0 ff ff vdpbf16ps -0x2000\(%edx\)\{1to16\},%zmm5,%zmm6\{%k7\}\{z\}
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_bf16.s b/gas/testsuite/gas/i386/avx512_bf16.s
new file mode 100644
index 0000000..74f60d2
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_bf16.s
@@ -0,0 +1,37 @@
+# Check 32bit AVX512_BF16 instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vcvtne2ps2bf16 %zmm4, %zmm5, %zmm6 #AVX512_BF16
+ vcvtne2ps2bf16 0x10000000(%esp, %esi, 8), %zmm5, %zmm6{%k7} #AVX512_BF16 MASK_ENABLING
+ vcvtne2ps2bf16 (%ecx){1to16}, %zmm5, %zmm6 #AVX512_BF16 BROADCAST_EN
+ vcvtne2ps2bf16 8128(%ecx), %zmm5, %zmm6 #AVX512_BF16 Disp8
+ vcvtne2ps2bf16 -8192(%edx){1to16}, %zmm5, %zmm6{%k7}{z} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 %zmm5, %ymm6 #AVX512_BF16
+ vcvtneps2bf16 0x10000000(%esp, %esi, 8), %ymm6{%k7} #AVX512_BF16 MASK_ENABLING
+ vcvtneps2bf16 (%ecx){1to16}, %ymm6 #AVX512_BF16 BROADCAST_EN
+ vcvtneps2bf16 8128(%ecx), %ymm6 #AVX512_BF16 Disp8
+ vcvtneps2bf16 -8192(%edx){1to16}, %ymm6{%k7}{z} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps %zmm4, %zmm5, %zmm6 #AVX512_BF16
+ vdpbf16ps 0x10000000(%esp, %esi, 8), %zmm5, %zmm6{%k7} #AVX512_BF16 MASK_ENABLING
+ vdpbf16ps (%ecx){1to16}, %zmm5, %zmm6 #AVX512_BF16 BROADCAST_EN
+ vdpbf16ps 8128(%ecx), %zmm5, %zmm6 #AVX512_BF16 Disp8
+ vdpbf16ps -8192(%edx){1to16}, %zmm5, %zmm6{%k7}{z} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+
+.intel_syntax noprefix
+ vcvtne2ps2bf16 zmm6, zmm5, zmm4 #AVX512_BF16
+ vcvtne2ps2bf16 zmm6{k7}, zmm5, ZMMWORD PTR [esp+esi*8+0x10000000] #AVX512_BF16 MASK_ENABLING
+ vcvtne2ps2bf16 zmm6, zmm5, DWORD PTR [ecx]{1to16} #AVX512_BF16 BROADCAST_EN
+ vcvtne2ps2bf16 zmm6, zmm5, ZMMWORD PTR [ecx+8128] #AVX512_BF16 Disp8
+ vcvtne2ps2bf16 zmm6{k7}{z}, zmm5, DWORD PTR [edx-8192]{1to16} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 ymm6, zmm5 #AVX512_BF16
+ vcvtneps2bf16 ymm6{k7}, ZMMWORD PTR [esp+esi*8+0x10000000] #AVX512_BF16 MASK_ENABLING
+ vcvtneps2bf16 ymm6, DWORD PTR [ecx]{1to16} #AVX512_BF16 BROADCAST_EN
+ vcvtneps2bf16 ymm6, ZMMWORD PTR [ecx+8128] #AVX512_BF16 Disp8
+ vcvtneps2bf16 ymm6{k7}{z}, DWORD PTR [edx-8192]{1to16} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps zmm6, zmm5, zmm4 #AVX512_BF16
+ vdpbf16ps zmm6{k7}, zmm5, ZMMWORD PTR [esp+esi*8+0x10000000] #AVX512_BF16 MASK_ENABLING
+ vdpbf16ps zmm6, zmm5, DWORD PTR [ecx]{1to16} #AVX512_BF16 BROADCAST_EN
+ vdpbf16ps zmm6, zmm5, ZMMWORD PTR [ecx+8128] #AVX512_BF16 Disp8
+ vdpbf16ps zmm6{k7}{z}, zmm5, DWORD PTR [edx-8192]{1to16} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
diff --git a/gas/testsuite/gas/i386/avx512_bf16_vl-inval.l b/gas/testsuite/gas/i386/avx512_bf16_vl-inval.l
new file mode 100644
index 0000000..dfd21d6
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_bf16_vl-inval.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:6: Error: .*
+.*:7: Error: .*
+.*:8: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
diff --git a/gas/testsuite/gas/i386/avx512_bf16_vl-inval.s b/gas/testsuite/gas/i386/avx512_bf16_vl-inval.s
new file mode 100644
index 0000000..e9e36b0
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_bf16_vl-inval.s
@@ -0,0 +1,13 @@
+# Check illegal AVX512{BF16,VL} instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vcvtneps2bf16 0x10000000(%rbp, %r14, 8), %xmm3{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vcvtneps2bf16 2032(%rcx), %xmm3 #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 4064(%rcx), %xmm3 #AVX512{BF16,VL} Disp8
+
+.intel_syntax noprefix
+ vcvtneps2bf16 xmm3{k7}, [rbp+r14*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vcvtneps2bf16 xmm3, [rcx+2032] #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 xmm3, [rcx+4064] #AVX512{BF16,VL} Disp8
diff --git a/gas/testsuite/gas/i386/avx512_bf16_vl.d b/gas/testsuite/gas/i386/avx512_bf16_vl.d
new file mode 100644
index 0000000..1467bc3
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_bf16_vl.d
@@ -0,0 +1,70 @@
+#as:
+#objdump: -dw
+#name: i386 BF16 VL insns
+#source: avx512_bf16_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 62 f2 57 28 72 f4 vcvtne2ps2bf16 %ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 57 08 72 f4 vcvtne2ps2bf16 %xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 57 2f 72 b4 f4 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 57 38 72 31 vcvtne2ps2bf16 \(%ecx\)\{1to8\},%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 57 28 72 71 7f vcvtne2ps2bf16 0xfe0\(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 57 bf 72 b2 00 f0 ff ff vcvtne2ps2bf16 -0x1000\(%edx\)\{1to8\},%ymm5,%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 57 0f 72 b4 f4 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 57 18 72 31 vcvtne2ps2bf16 \(%ecx\)\{1to4\},%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 57 08 72 71 7f vcvtne2ps2bf16 0x7f0\(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 57 9f 72 b2 00 f8 ff ff vcvtne2ps2bf16 -0x800\(%edx\)\{1to4\},%xmm5,%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 7e 08 72 f5 vcvtneps2bf16 %xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e 28 72 f5 vcvtneps2bf16 %ymm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e 0f 72 b4 f4 00 00 00 10 vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 7e 18 72 31 vcvtneps2bf16 \(%ecx\)\{1to4\},%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e 08 72 71 7f vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e 9f 72 b2 00 f8 ff ff vcvtneps2bf16 -0x800\(%edx\)\{1to4\},%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 7e 38 72 31 vcvtneps2bf16 \(%ecx\)\{1to8\},%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e 28 72 71 7f vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e bf 72 b2 00 f0 ff ff vcvtneps2bf16 -0x1000\(%edx\)\{1to8\},%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 56 28 52 f4 vdpbf16ps %ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 56 08 52 f4 vdpbf16ps %xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 56 2f 52 b4 f4 00 00 00 10 vdpbf16ps 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 56 38 52 31 vdpbf16ps \(%ecx\)\{1to8\},%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 56 28 52 71 7f vdpbf16ps 0xfe0\(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 56 bf 52 b2 00 f0 ff ff vdpbf16ps -0x1000\(%edx\)\{1to8\},%ymm5,%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 56 0f 52 b4 f4 00 00 00 10 vdpbf16ps 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 56 18 52 31 vdpbf16ps \(%ecx\)\{1to4\},%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 56 08 52 71 7f vdpbf16ps 0x7f0\(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 56 9f 52 b2 00 f8 ff ff vdpbf16ps -0x800\(%edx\)\{1to4\},%xmm5,%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 57 28 72 f4 vcvtne2ps2bf16 %ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 57 08 72 f4 vcvtne2ps2bf16 %xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 57 2f 72 b4 f4 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 57 38 72 31 vcvtne2ps2bf16 \(%ecx\)\{1to8\},%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 57 28 72 71 7f vcvtne2ps2bf16 0xfe0\(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 57 bf 72 b2 00 f0 ff ff vcvtne2ps2bf16 -0x1000\(%edx\)\{1to8\},%ymm5,%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 57 0f 72 b4 f4 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 57 18 72 31 vcvtne2ps2bf16 \(%ecx\)\{1to4\},%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 57 08 72 71 7f vcvtne2ps2bf16 0x7f0\(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 57 9f 72 b2 00 f8 ff ff vcvtne2ps2bf16 -0x800\(%edx\)\{1to4\},%xmm5,%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 7e 08 72 f5 vcvtneps2bf16 %xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e 28 72 f5 vcvtneps2bf16 %ymm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e 0f 72 b4 f4 00 00 00 10 vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 7e 18 72 31 vcvtneps2bf16 \(%ecx\)\{1to4\},%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e 08 72 71 7f vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e 9f 72 b2 00 f8 ff ff vcvtneps2bf16 -0x800\(%edx\)\{1to4\},%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 7e 38 72 31 vcvtneps2bf16 \(%ecx\)\{1to8\},%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e 28 72 71 7f vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: 62 f2 7e bf 72 b2 00 f0 ff ff vcvtneps2bf16 -0x1000\(%edx\)\{1to8\},%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 56 28 52 f4 vdpbf16ps %ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 56 08 52 f4 vdpbf16ps %xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 56 2f 52 b4 f4 00 00 00 10 vdpbf16ps 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 56 38 52 31 vdpbf16ps \(%ecx\)\{1to8\},%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 56 28 52 71 7f vdpbf16ps 0xfe0\(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: 62 f2 56 bf 52 b2 00 f0 ff ff vdpbf16ps -0x1000\(%edx\)\{1to8\},%ymm5,%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 f2 56 0f 52 b4 f4 00 00 00 10 vdpbf16ps 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 56 18 52 31 vdpbf16ps \(%ecx\)\{1to4\},%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 56 08 52 71 7f vdpbf16ps 0x7f0\(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: 62 f2 56 9f 52 b2 00 f8 ff ff vdpbf16ps -0x800\(%edx\)\{1to4\},%xmm5,%xmm6\{%k7\}\{z\}
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_bf16_vl.s b/gas/testsuite/gas/i386/avx512_bf16_vl.s
new file mode 100644
index 0000000..7872765
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_bf16_vl.s
@@ -0,0 +1,65 @@
+# Check 32bit AVX512{BF16,VL} instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vcvtne2ps2bf16 %ymm4, %ymm5, %ymm6 #AVX512{BF16,VL}
+ vcvtne2ps2bf16 %xmm4, %xmm5, %xmm6 #AVX512{BF16,VL}
+ vcvtne2ps2bf16 0x10000000(%esp, %esi, 8), %ymm5, %ymm6{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vcvtne2ps2bf16 (%ecx){1to8}, %ymm5, %ymm6 #AVX512{BF16,VL} BROADCAST_EN
+ vcvtne2ps2bf16 4064(%ecx), %ymm5, %ymm6 #AVX512{BF16,VL} Disp8
+ vcvtne2ps2bf16 -4096(%edx){1to8}, %ymm5, %ymm6{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtne2ps2bf16 0x10000000(%esp, %esi, 8), %xmm5, %xmm6{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vcvtne2ps2bf16 (%ecx){1to4}, %xmm5, %xmm6 #AVX512{BF16,VL} BROADCAST_EN
+ vcvtne2ps2bf16 2032(%ecx), %xmm5, %xmm6 #AVX512{BF16,VL} Disp8
+ vcvtne2ps2bf16 -2048(%edx){1to4}, %xmm5, %xmm6{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 %xmm5, %xmm6 #AVX512{BF16,VL}
+ vcvtneps2bf16 %ymm5, %xmm6 #AVX512{BF16,VL}
+ vcvtneps2bf16x 0x10000000(%esp, %esi, 8), %xmm6{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vcvtneps2bf16 (%ecx){1to4}, %xmm6 #AVX512{BF16,VL} BROADCAST_EN
+ vcvtneps2bf16x 2032(%ecx), %xmm6 #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 -2048(%edx){1to4}, %xmm6{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 (%ecx){1to8}, %xmm6 #AVX512{BF16,VL} BROADCAST_EN
+ vcvtneps2bf16y 4064(%ecx), %xmm6 #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 -4096(%edx){1to8}, %xmm6{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps %ymm4, %ymm5, %ymm6 #AVX512{BF16,VL}
+ vdpbf16ps %xmm4, %xmm5, %xmm6 #AVX512{BF16,VL}
+ vdpbf16ps 0x10000000(%esp, %esi, 8), %ymm5, %ymm6{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vdpbf16ps (%ecx){1to8}, %ymm5, %ymm6 #AVX512{BF16,VL} BROADCAST_EN
+ vdpbf16ps 4064(%ecx), %ymm5, %ymm6 #AVX512{BF16,VL} Disp8
+ vdpbf16ps -4096(%edx){1to8}, %ymm5, %ymm6{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps 0x10000000(%esp, %esi, 8), %xmm5, %xmm6{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vdpbf16ps (%ecx){1to4}, %xmm5, %xmm6 #AVX512{BF16,VL} BROADCAST_EN
+ vdpbf16ps 2032(%ecx), %xmm5, %xmm6 #AVX512{BF16,VL} Disp8
+ vdpbf16ps -2048(%edx){1to4}, %xmm5, %xmm6{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+
+.intel_syntax noprefix
+ vcvtne2ps2bf16 ymm6, ymm5, ymm4 #AVX512{BF16,VL}
+ vcvtne2ps2bf16 xmm6, xmm5, xmm4 #AVX512{BF16,VL}
+ vcvtne2ps2bf16 ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vcvtne2ps2bf16 ymm6, ymm5, DWORD PTR [ecx]{1to8} #AVX512{BF16,VL} BROADCAST_EN
+ vcvtne2ps2bf16 ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX512{BF16,VL} Disp8
+ vcvtne2ps2bf16 ymm6{k7}{z}, ymm5, DWORD PTR [edx-4096]{1to8} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtne2ps2bf16 xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vcvtne2ps2bf16 xmm6, xmm5, DWORD PTR [ecx]{1to4} #AVX512{BF16,VL} BROADCAST_EN
+ vcvtne2ps2bf16 xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX512{BF16,VL} Disp8
+ vcvtne2ps2bf16 xmm6{k7}{z}, xmm5, DWORD PTR [edx-2048]{1to4} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 xmm6, xmm5 #AVX512{BF16,VL}
+ vcvtneps2bf16 xmm6, ymm5 #AVX512{BF16,VL}
+ vcvtneps2bf16 xmm6{k7}, XMMWORD PTR [esp+esi*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vcvtneps2bf16 xmm6, DWORD PTR [ecx]{1to4} #AVX512{BF16,VL} BROADCAST_EN
+ vcvtneps2bf16 xmm6, XMMWORD PTR [ecx+2032] #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 xmm6{k7}{z}, DWORD PTR [edx-2048]{1to4} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 xmm6, DWORD PTR [ecx]{1to8} #AVX512{BF16,VL} BROADCAST_EN
+ vcvtneps2bf16 xmm6, YMMWORD PTR [ecx+4064] #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 xmm6{k7}{z}, DWORD PTR [edx-4096]{1to8} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps ymm6, ymm5, ymm4 #AVX512{BF16,VL}
+ vdpbf16ps xmm6, xmm5, xmm4 #AVX512{BF16,VL}
+ vdpbf16ps ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vdpbf16ps ymm6, ymm5, DWORD PTR [ecx]{1to8} #AVX512{BF16,VL} BROADCAST_EN
+ vdpbf16ps ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX512{BF16,VL} Disp8
+ vdpbf16ps ymm6{k7}{z}, ymm5, DWORD PTR [edx-4096]{1to8} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vdpbf16ps xmm6, xmm5, DWORD PTR [ecx]{1to4} #AVX512{BF16,VL} BROADCAST_EN
+ vdpbf16ps xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX512{BF16,VL} Disp8
+ vdpbf16ps xmm6{k7}{z}, xmm5, DWORD PTR [edx-2048]{1to4} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index afb6116..1dd1313 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -423,6 +423,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "avx512bitalg-intel"
run_dump_test "avx512bitalg_vl"
run_dump_test "avx512bitalg_vl-intel"
+ run_dump_test "avx512_bf16"
+ run_dump_test "avx512_bf16_vl"
+ run_list_test "avx512_bf16_vl-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "disassem"
@@ -937,6 +940,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-avx512bitalg-intel"
run_dump_test "x86-64-avx512bitalg_vl"
run_dump_test "x86-64-avx512bitalg_vl-intel"
+ run_dump_test "x86-64-avx512_bf16"
+ run_dump_test "x86-64-avx512_bf16_vl"
+ run_list_test "x86-64-avx512_bf16_vl-inval"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bf16.d b/gas/testsuite/gas/i386/x86-64-avx512_bf16.d
new file mode 100644
index 0000000..2b3c27f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_bf16.d
@@ -0,0 +1,42 @@
+#as:
+#objdump: -dw
+#name: x86-64 BF16 insns
+#source: x86-64-avx512_bf16.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 62 02 17 40 72 f4 vcvtne2ps2bf16 %zmm28,%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 22 17 47 72 b4 f5 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%rbp,%r14,8\),%zmm29,%zmm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 17 50 72 31 vcvtne2ps2bf16 \(%r9\)\{1to16\},%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 62 17 40 72 71 7f vcvtne2ps2bf16 0x1fc0\(%rcx\),%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 62 17 d7 72 b2 00 e0 ff ff vcvtne2ps2bf16 -0x2000\(%rdx\)\{1to16\},%zmm29,%zmm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 02 7e 48 72 f5 vcvtneps2bf16 %zmm29,%ymm30
+[ ]*[a-f0-9]+: 62 22 7e 4f 72 b4 f5 00 00 00 10 vcvtneps2bf16 0x10000000\(%rbp,%r14,8\),%ymm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 7e 58 72 31 vcvtneps2bf16 \(%r9\)\{1to16\},%ymm30
+[ ]*[a-f0-9]+: 62 62 7e 48 72 71 7f vcvtneps2bf16 0x1fc0\(%rcx\),%ymm30
+[ ]*[a-f0-9]+: 62 62 7e df 72 b2 00 e0 ff ff vcvtneps2bf16 -0x2000\(%rdx\)\{1to16\},%ymm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 02 16 40 52 f4 vdpbf16ps %zmm28,%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 22 16 47 52 b4 f5 00 00 00 10 vdpbf16ps 0x10000000\(%rbp,%r14,8\),%zmm29,%zmm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 16 50 52 31 vdpbf16ps \(%r9\)\{1to16\},%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 62 16 40 52 71 7f vdpbf16ps 0x1fc0\(%rcx\),%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 62 16 d7 52 b2 00 e0 ff ff vdpbf16ps -0x2000\(%rdx\)\{1to16\},%zmm29,%zmm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 02 17 40 72 f4 vcvtne2ps2bf16 %zmm28,%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 22 17 47 72 b4 f5 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%rbp,%r14,8\),%zmm29,%zmm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 17 50 72 31 vcvtne2ps2bf16 \(%r9\)\{1to16\},%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 62 17 40 72 71 7f vcvtne2ps2bf16 0x1fc0\(%rcx\),%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 62 17 d7 72 b2 00 e0 ff ff vcvtne2ps2bf16 -0x2000\(%rdx\)\{1to16\},%zmm29,%zmm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 02 7e 48 72 f5 vcvtneps2bf16 %zmm29,%ymm30
+[ ]*[a-f0-9]+: 62 22 7e 4f 72 b4 f5 00 00 00 10 vcvtneps2bf16 0x10000000\(%rbp,%r14,8\),%ymm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 7e 58 72 31 vcvtneps2bf16 \(%r9\)\{1to16\},%ymm30
+[ ]*[a-f0-9]+: 62 62 7e 48 72 71 7f vcvtneps2bf16 0x1fc0\(%rcx\),%ymm30
+[ ]*[a-f0-9]+: 62 62 7e df 72 b2 00 e0 ff ff vcvtneps2bf16 -0x2000\(%rdx\)\{1to16\},%ymm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 02 16 40 52 f4 vdpbf16ps %zmm28,%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 22 16 47 52 b4 f5 00 00 00 10 vdpbf16ps 0x10000000\(%rbp,%r14,8\),%zmm29,%zmm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 16 50 52 31 vdpbf16ps \(%r9\)\{1to16\},%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 62 16 40 52 71 7f vdpbf16ps 0x1fc0\(%rcx\),%zmm29,%zmm30
+[ ]*[a-f0-9]+: 62 62 16 d7 52 b2 00 e0 ff ff vdpbf16ps -0x2000\(%rdx\)\{1to16\},%zmm29,%zmm30\{%k7\}\{z\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bf16.s b/gas/testsuite/gas/i386/x86-64-avx512_bf16.s
new file mode 100644
index 0000000..5dc3b5e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_bf16.s
@@ -0,0 +1,37 @@
+# Check 64bit AVX512_BF16 instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vcvtne2ps2bf16 %zmm28, %zmm29, %zmm30 #AVX512_BF16
+ vcvtne2ps2bf16 0x10000000(%rbp, %r14, 8), %zmm29, %zmm30{%k7} #AVX512_BF16 MASK_ENABLING
+ vcvtne2ps2bf16 (%r9){1to16}, %zmm29, %zmm30 #AVX512_BF16 BROADCAST_EN
+ vcvtne2ps2bf16 8128(%rcx), %zmm29, %zmm30 #AVX512_BF16 Disp8
+ vcvtne2ps2bf16 -8192(%rdx){1to16}, %zmm29, %zmm30{%k7}{z} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 %zmm29, %ymm30 #AVX512_BF16
+ vcvtneps2bf16 0x10000000(%rbp, %r14, 8), %ymm30{%k7} #AVX512_BF16 MASK_ENABLING
+ vcvtneps2bf16 (%r9){1to16}, %ymm30 #AVX512_BF16 BROADCAST_EN
+ vcvtneps2bf16 8128(%rcx), %ymm30 #AVX512_BF16 Disp8
+ vcvtneps2bf16 -8192(%rdx){1to16}, %ymm30{%k7}{z} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps %zmm28, %zmm29, %zmm30 #AVX512_BF16
+ vdpbf16ps 0x10000000(%rbp, %r14, 8), %zmm29, %zmm30{%k7} #AVX512_BF16 MASK_ENABLING
+ vdpbf16ps (%r9){1to16}, %zmm29, %zmm30 #AVX512_BF16 BROADCAST_EN
+ vdpbf16ps 8128(%rcx), %zmm29, %zmm30 #AVX512_BF16 Disp8
+ vdpbf16ps -8192(%rdx){1to16}, %zmm29, %zmm30{%k7}{z} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+
+.intel_syntax noprefix
+ vcvtne2ps2bf16 zmm30, zmm29, zmm28 #AVX512_BF16
+ vcvtne2ps2bf16 zmm30{k7}, zmm29, ZMMWORD PTR [rbp+r14*8+0x10000000] #AVX512_BF16 MASK_ENABLING
+ vcvtne2ps2bf16 zmm30, zmm29, DWORD PTR [r9]{1to16} #AVX512_BF16 BROADCAST_EN
+ vcvtne2ps2bf16 zmm30, zmm29, ZMMWORD PTR [rcx+8128] #AVX512_BF16 Disp8
+ vcvtne2ps2bf16 zmm30{k7}{z}, zmm29, DWORD PTR [rdx-8192]{1to16} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 ymm30, zmm29 #AVX512_BF16
+ vcvtneps2bf16 ymm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000] #AVX512_BF16 MASK_ENABLING
+ vcvtneps2bf16 ymm30, DWORD PTR [r9]{1to16} #AVX512_BF16 BROADCAST_EN
+ vcvtneps2bf16 ymm30, ZMMWORD PTR [rcx+8128] #AVX512_BF16 Disp8
+ vcvtneps2bf16 ymm30{k7}{z}, DWORD PTR [rdx-8192]{1to16} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps zmm30, zmm29, zmm28 #AVX512_BF16
+ vdpbf16ps zmm30{k7}, zmm29, ZMMWORD PTR [rbp+r14*8+0x10000000] #AVX512_BF16 MASK_ENABLING
+ vdpbf16ps zmm30, zmm29, DWORD PTR [r9]{1to16} #AVX512_BF16 BROADCAST_EN
+ vdpbf16ps zmm30, zmm29, ZMMWORD PTR [rcx+8128] #AVX512_BF16 Disp8
+ vdpbf16ps zmm30{k7}{z}, zmm29, DWORD PTR [rdx-8192]{1to16} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l b/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l
new file mode 100644
index 0000000..dfd21d6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:6: Error: .*
+.*:7: Error: .*
+.*:8: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s b/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s
new file mode 100644
index 0000000..045511b
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s
@@ -0,0 +1,13 @@
+# Check illegal 64bit AVX512{BF16,VL} instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vcvtneps2bf16 0x10000000(%rbp, %r14, 8), %xmm30{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vcvtneps2bf16 2032(%rcx), %xmm30 #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 4064(%rcx), %xmm30 #AVX512{BF16,VL} Disp8
+
+.intel_syntax noprefix
+ vcvtneps2bf16 xmm30{k7}, [rbp+r14*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vcvtneps2bf16 xmm30, [rcx+2032] #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 xmm30, [rcx+4064] #AVX512{BF16,VL} Disp8
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.d b/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.d
new file mode 100644
index 0000000..43810a6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.d
@@ -0,0 +1,70 @@
+#as:
+#objdump: -dw
+#name: x86-64 BF16 VL insns
+#source: x86-64-avx512_bf16_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 62 02 17 20 72 f4 vcvtne2ps2bf16 %ymm28,%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 02 17 00 72 f4 vcvtne2ps2bf16 %xmm28,%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 22 17 27 72 b4 f5 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%rbp,%r14,8\),%ymm29,%ymm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 17 30 72 31 vcvtne2ps2bf16 \(%r9\)\{1to8\},%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 62 17 20 72 71 7f vcvtne2ps2bf16 0xfe0\(%rcx\),%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 62 17 b7 72 b2 00 f0 ff ff vcvtne2ps2bf16 -0x1000\(%rdx\)\{1to8\},%ymm29,%ymm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 22 17 07 72 b4 f5 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%rbp,%r14,8\),%xmm29,%xmm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 17 10 72 31 vcvtne2ps2bf16 \(%r9\)\{1to4\},%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 62 17 00 72 71 7f vcvtne2ps2bf16 0x7f0\(%rcx\),%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 62 17 97 72 a2 00 f8 ff ff vcvtne2ps2bf16 -0x800\(%rdx\)\{1to4\},%xmm29,%xmm28\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 02 7e 08 72 f5 vcvtneps2bf16 %xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 02 7e 28 72 f5 vcvtneps2bf16 %ymm29,%xmm30
+[ ]*[a-f0-9]+: 62 22 7e 0f 72 b4 f5 00 00 00 10 vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\}
+[ ]*[a-f0-9]+: 62 c2 7e 18 72 29 vcvtneps2bf16 \(%r9\)\{1to4\},%xmm21
+[ ]*[a-f0-9]+: 62 62 7e 08 72 71 7f vcvtneps2bf16x 0x7f0\(%rcx\),%xmm30
+[ ]*[a-f0-9]+: 62 62 7e 9f 72 aa 00 f8 ff ff vcvtneps2bf16 -0x800\(%rdx\)\{1to4\},%xmm29\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 c2 7e 38 72 31 vcvtneps2bf16 \(%r9\)\{1to8\},%xmm22
+[ ]*[a-f0-9]+: 62 e2 7e 28 72 79 7f vcvtneps2bf16y 0xfe0\(%rcx\),%xmm23
+[ ]*[a-f0-9]+: 62 62 7e bf 72 9a 00 f0 ff ff vcvtneps2bf16 -0x1000\(%rdx\)\{1to8\},%xmm27\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 02 16 20 52 f4 vdpbf16ps %ymm28,%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 02 16 00 52 f4 vdpbf16ps %xmm28,%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 22 16 27 52 b4 f5 00 00 00 10 vdpbf16ps 0x10000000\(%rbp,%r14,8\),%ymm29,%ymm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 16 30 52 31 vdpbf16ps \(%r9\)\{1to8\},%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 62 16 20 52 71 7f vdpbf16ps 0xfe0\(%rcx\),%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 62 16 b7 52 b2 00 f0 ff ff vdpbf16ps -0x1000\(%rdx\)\{1to8\},%ymm29,%ymm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 22 16 07 52 b4 f5 00 00 00 10 vdpbf16ps 0x10000000\(%rbp,%r14,8\),%xmm29,%xmm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 16 10 52 31 vdpbf16ps \(%r9\)\{1to4\},%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 62 16 00 52 71 7f vdpbf16ps 0x7f0\(%rcx\),%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 62 16 97 52 b2 00 f8 ff ff vdpbf16ps -0x800\(%rdx\)\{1to4\},%xmm29,%xmm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 02 17 20 72 f4 vcvtne2ps2bf16 %ymm28,%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 02 17 00 72 f4 vcvtne2ps2bf16 %xmm28,%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 22 17 27 72 b4 f5 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%rbp,%r14,8\),%ymm29,%ymm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 17 30 72 31 vcvtne2ps2bf16 \(%r9\)\{1to8\},%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 62 17 20 72 71 7f vcvtne2ps2bf16 0xfe0\(%rcx\),%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 62 17 b7 72 b2 00 f0 ff ff vcvtne2ps2bf16 -0x1000\(%rdx\)\{1to8\},%ymm29,%ymm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 22 17 07 72 b4 f5 00 00 00 10 vcvtne2ps2bf16 0x10000000\(%rbp,%r14,8\),%xmm29,%xmm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 17 10 72 31 vcvtne2ps2bf16 \(%r9\)\{1to4\},%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 62 17 00 72 71 7f vcvtne2ps2bf16 0x7f0\(%rcx\),%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 62 17 97 72 b2 00 f8 ff ff vcvtne2ps2bf16 -0x800\(%rdx\)\{1to4\},%xmm29,%xmm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 02 7e 08 72 f5 vcvtneps2bf16 %xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 02 7e 28 72 f5 vcvtneps2bf16 %ymm29,%xmm30
+[ ]*[a-f0-9]+: 62 22 7e 0f 72 b4 f5 00 00 00 10 vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 7e 18 72 09 vcvtneps2bf16 \(%r9\)\{1to4\},%xmm25
+[ ]*[a-f0-9]+: 62 62 7e 08 72 71 7f vcvtneps2bf16x 0x7f0\(%rcx\),%xmm30
+[ ]*[a-f0-9]+: 62 62 7e 9f 72 b2 00 f8 ff ff vcvtneps2bf16 -0x800\(%rdx\)\{1to4\},%xmm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 42 7e 38 72 01 vcvtneps2bf16 \(%r9\)\{1to8\},%xmm24
+[ ]*[a-f0-9]+: 62 62 7e 28 72 71 7f vcvtneps2bf16y 0xfe0\(%rcx\),%xmm30
+[ ]*[a-f0-9]+: 62 62 7e bf 72 b2 00 f0 ff ff vcvtneps2bf16 -0x1000\(%rdx\)\{1to8\},%xmm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 02 16 20 52 f4 vdpbf16ps %ymm28,%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 02 16 00 52 f4 vdpbf16ps %xmm28,%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 22 16 27 52 b4 f5 00 00 00 10 vdpbf16ps 0x10000000\(%rbp,%r14,8\),%ymm29,%ymm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 16 30 52 31 vdpbf16ps \(%r9\)\{1to8\},%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 62 16 20 52 71 7f vdpbf16ps 0xfe0\(%rcx\),%ymm29,%ymm30
+[ ]*[a-f0-9]+: 62 62 16 b7 52 b2 00 f0 ff ff vdpbf16ps -0x1000\(%rdx\)\{1to8\},%ymm29,%ymm30\{%k7\}\{z\}
+[ ]*[a-f0-9]+: 62 22 16 07 52 b4 f5 00 00 00 10 vdpbf16ps 0x10000000\(%rbp,%r14,8\),%xmm29,%xmm30\{%k7\}
+[ ]*[a-f0-9]+: 62 42 16 10 52 31 vdpbf16ps \(%r9\)\{1to4\},%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 62 16 00 52 71 7f vdpbf16ps 0x7f0\(%rcx\),%xmm29,%xmm30
+[ ]*[a-f0-9]+: 62 62 16 97 52 b2 00 f8 ff ff vdpbf16ps -0x800\(%rdx\)\{1to4\},%xmm29,%xmm30\{%k7\}\{z\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.s b/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.s
new file mode 100644
index 0000000..e7c3a0a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.s
@@ -0,0 +1,65 @@
+# Check 64bit AVX512{BF16,VL} instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vcvtne2ps2bf16 %ymm28, %ymm29, %ymm30 #AVX512{BF16,VL}
+ vcvtne2ps2bf16 %xmm28, %xmm29, %xmm30 #AVX512{BF16,VL}
+ vcvtne2ps2bf16 0x10000000(%rbp, %r14, 8), %ymm29, %ymm30{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vcvtne2ps2bf16 (%r9){1to8}, %ymm29, %ymm30 #AVX512{BF16,VL} BROADCAST_EN
+ vcvtne2ps2bf16 4064(%rcx), %ymm29, %ymm30 #AVX512{BF16,VL} Disp8
+ vcvtne2ps2bf16 -4096(%rdx){1to8}, %ymm29, %ymm30{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtne2ps2bf16 0x10000000(%rbp, %r14, 8), %xmm29, %xmm30{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vcvtne2ps2bf16 (%r9){1to4}, %xmm29, %xmm30 #AVX512{BF16,VL} BROADCAST_EN
+ vcvtne2ps2bf16 2032(%rcx), %xmm29, %xmm30 #AVX512{BF16,VL} Disp8
+ vcvtne2ps2bf16 -2048(%rdx){1to4}, %xmm29, %xmm28{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 %xmm29, %xmm30 #AVX512{BF16,VL}
+ vcvtneps2bf16 %ymm29, %xmm30 #AVX512{BF16,VL}
+ vcvtneps2bf16x 0x10000000(%rbp, %r14, 8), %xmm30{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vcvtneps2bf16 (%r9){1to4}, %xmm21 #AVX512{BF16,VL} BROADCAST_EN
+ vcvtneps2bf16x 2032(%rcx), %xmm30 #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 -2048(%rdx){1to4}, %xmm29{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 (%r9){1to8}, %xmm22 #AVX512{BF16,VL} BROADCAST_EN
+ vcvtneps2bf16y 4064(%rcx), %xmm23 #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 -4096(%rdx){1to8}, %xmm27{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps %ymm28, %ymm29, %ymm30 #AVX512{BF16,VL}
+ vdpbf16ps %xmm28, %xmm29, %xmm30 #AVX512{BF16,VL}
+ vdpbf16ps 0x10000000(%rbp, %r14, 8), %ymm29, %ymm30{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vdpbf16ps (%r9){1to8}, %ymm29, %ymm30 #AVX512{BF16,VL} BROADCAST_EN
+ vdpbf16ps 4064(%rcx), %ymm29, %ymm30 #AVX512{BF16,VL} Disp8
+ vdpbf16ps -4096(%rdx){1to8}, %ymm29, %ymm30{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps 0x10000000(%rbp, %r14, 8), %xmm29, %xmm30{%k7} #AVX512{BF16,VL} MASK_ENABLING
+ vdpbf16ps (%r9){1to4}, %xmm29, %xmm30 #AVX512{BF16,VL} BROADCAST_EN
+ vdpbf16ps 2032(%rcx), %xmm29, %xmm30 #AVX512{BF16,VL} Disp8
+ vdpbf16ps -2048(%rdx){1to4}, %xmm29, %xmm30{%k7}{z} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+
+.intel_syntax noprefix
+ vcvtne2ps2bf16 ymm30, ymm29, ymm28 #AVX512{BF16,VL}
+ vcvtne2ps2bf16 xmm30, xmm29, xmm28 #AVX512{BF16,VL}
+ vcvtne2ps2bf16 ymm30{k7}, ymm29, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vcvtne2ps2bf16 ymm30, ymm29, DWORD PTR [r9]{1to8} #AVX512{BF16,VL} BROADCAST_EN
+ vcvtne2ps2bf16 ymm30, ymm29, YMMWORD PTR [rcx+4064] #AVX512{BF16,VL} Disp8
+ vcvtne2ps2bf16 ymm30{k7}{z}, ymm29, DWORD PTR [rdx-4096]{1to8} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtne2ps2bf16 xmm30{k7}, xmm29, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vcvtne2ps2bf16 xmm30, xmm29, DWORD PTR [r9]{1to4} #AVX512{BF16,VL} BROADCAST_EN
+ vcvtne2ps2bf16 xmm30, xmm29, XMMWORD PTR [rcx+2032] #AVX512{BF16,VL} Disp8
+ vcvtne2ps2bf16 xmm30{k7}{z}, xmm29, DWORD PTR [rdx-2048]{1to4} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 xmm30, xmm29 #AVX512{BF16,VL}
+ vcvtneps2bf16 xmm30, ymm29 #AVX512{BF16,VL}
+ vcvtneps2bf16 xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vcvtneps2bf16 xmm25, DWORD PTR [r9]{1to4} #AVX512{BF16,VL} BROADCAST_EN
+ vcvtneps2bf16 xmm30, XMMWORD PTR [rcx+2032] #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 xmm30{k7}{z}, DWORD PTR [rdx-2048]{1to4} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vcvtneps2bf16 xmm24, DWORD PTR [r9]{1to8} #AVX512{BF16,VL} BROADCAST_EN
+ vcvtneps2bf16 xmm30, YMMWORD PTR [rcx+4064] #AVX512{BF16,VL} Disp8
+ vcvtneps2bf16 xmm30{k7}{z}, DWORD PTR [rdx-4096]{1to8} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps ymm30, ymm29, ymm28 #AVX512{BF16,VL}
+ vdpbf16ps xmm30, xmm29, xmm28 #AVX512{BF16,VL}
+ vdpbf16ps ymm30{k7}, ymm29, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vdpbf16ps ymm30, ymm29, DWORD PTR [r9]{1to8} #AVX512{BF16,VL} BROADCAST_EN
+ vdpbf16ps ymm30, ymm29, YMMWORD PTR [rcx+4064] #AVX512{BF16,VL} Disp8
+ vdpbf16ps ymm30{k7}{z}, ymm29, DWORD PTR [rdx-4096]{1to8} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
+ vdpbf16ps xmm30{k7}, xmm29, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX512{BF16,VL} MASK_ENABLING
+ vdpbf16ps xmm30, xmm29, DWORD PTR [r9]{1to4} #AVX512{BF16,VL} BROADCAST_EN
+ vdpbf16ps xmm30, xmm29, XMMWORD PTR [rcx+2032] #AVX512{BF16,VL} Disp8
+ vdpbf16ps xmm30{k7}{z}, xmm29, DWORD PTR [rdx-2048]{1to4} #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3a1895b..670bf53 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
+
+ * i386-dis-evex.h (evex_table): Updated to support BF16
+ instructions.
+ * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
+ and EVEX_W_0F3872_P_3.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
+ (cpu_flags): Add bitfield for CpuAVX512_BF16.
+ * i386-opc.h (enum): Add CpuAVX512_BF16.
+ (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
+ * i386-opc.tbl: Add AVX512 BF16 instructions.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
2019-04-05 Alan Modra <amodra@gmail.com>
* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index dec7fc4..9fea25d 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -2020,7 +2020,7 @@ static const struct dis386 evex_table[][256] = {
/* PREFIX_EVEX_0F3852 */
{
{ Bad_Opcode },
- { Bad_Opcode },
+ { VEX_W_TABLE (EVEX_W_0F3852_P_1) },
{ "vpdpwssd", { XM, Vex, EXx }, 0 },
{ "vp4dpwssd", { XM, Vex, EXxmm }, 0 },
},
@@ -2112,8 +2112,9 @@ static const struct dis386 evex_table[][256] = {
/* PREFIX_EVEX_0F3872 */
{
{ Bad_Opcode },
- { Bad_Opcode },
+ { VEX_W_TABLE (EVEX_W_0F3872_P_1) },
{ VEX_W_TABLE (EVEX_W_0F3872_P_2) },
+ { VEX_W_TABLE (EVEX_W_0F3872_P_3) },
},
/* PREFIX_EVEX_0F3873 */
{
@@ -3705,6 +3706,11 @@ static const struct dis386 evex_table[][256] = {
{ "vpmulld", { XM, Vex, EXx }, 0 },
{ "vpmullq", { XM, Vex, EXx }, 0 },
},
+ /* EVEX_W_0F3852_P_1 */
+ {
+ { "vdpbf16ps", { XM, Vex, EXx }, 0 },
+ { Bad_Opcode },
+ },
/* EVEX_W_0F3854_P_2 */
{
{ "vpopcntb", { XM, EXx }, 0 },
@@ -3759,11 +3765,21 @@ static const struct dis386 evex_table[][256] = {
{ "vpshldvd", { XM, Vex, EXx }, 0 },
{ "vpshldvq", { XM, Vex, EXx }, 0 },
},
+ /* EVEX_W_0F3872_P_1 */
+ {
+ { "vcvtneps2bf16%XY", { XMxmmq, EXx }, 0 },
+ { Bad_Opcode },
+ },
/* EVEX_W_0F3872_P_2 */
{
{ Bad_Opcode },
{ "vpshrdvw", { XM, Vex, EXx }, 0 },
},
+ /* EVEX_W_0F3872_P_3 */
+ {
+ { "vcvtne2ps2bf16", { XM, Vex, EXx}, 0 },
+ { Bad_Opcode },
+ },
/* EVEX_W_0F3873_P_2 */
{
{ "vpshrdvd", { XM, Vex, EXx }, 0 },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 8320924..1ba7b4f 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -2189,6 +2189,7 @@ enum
EVEX_W_0F3839_P_1,
EVEX_W_0F383A_P_1,
EVEX_W_0F3840_P_2,
+ EVEX_W_0F3852_P_1,
EVEX_W_0F3854_P_2,
EVEX_W_0F3855_P_2,
EVEX_W_0F3858_P_2,
@@ -2200,7 +2201,9 @@ enum
EVEX_W_0F3866_P_2,
EVEX_W_0F3870_P_2,
EVEX_W_0F3871_P_2,
+ EVEX_W_0F3872_P_1,
EVEX_W_0F3872_P_2,
+ EVEX_W_0F3872_P_3,
EVEX_W_0F3873_P_2,
EVEX_W_0F3875_P_2,
EVEX_W_0F3878_P_2,
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 2b93063..847a7bb 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -231,6 +231,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX512F_FLAGS|CpuAVX512_VNNI" },
{ "CPU_AVX512_BITALG_FLAGS",
"CPU_AVX512F_FLAGS|CpuAVX512_BITALG" },
+ { "CPU_AVX512_BF16_FLAGS",
+ "CPU_AVX512F_FLAGS|CpuAVX512_BF16" },
{ "CPU_L1OM_FLAGS",
"unknown" },
{ "CPU_K1OM_FLAGS",
@@ -324,7 +326,7 @@ static initializer cpu_flag_init[] =
{ "CPU_ANY_AVX2_FLAGS",
"CPU_ANY_AVX512F_FLAGS|CpuAVX2" },
{ "CPU_ANY_AVX512F_FLAGS",
- "CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG" },
+ "CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16" },
{ "CPU_ANY_AVX512CD_FLAGS",
"CpuAVX512CD" },
{ "CPU_ANY_AVX512ER_FLAGS",
@@ -357,6 +359,8 @@ static initializer cpu_flag_init[] =
"CpuAVX512_VNNI" },
{ "CPU_ANY_AVX512_BITALG_FLAGS",
"CpuAVX512_BITALG" },
+ { "CPU_ANY_AVX512_BF16_FLAGS",
+ "CpuAVX512_BF16" },
{ "CPU_ANY_MOVDIRI_FLAGS",
"CpuMOVDIRI" },
{ "CPU_ANY_MOVDIR64B_FLAGS",
@@ -578,6 +582,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX512_VBMI2),
BITFIELD (CpuAVX512_VNNI),
BITFIELD (CpuAVX512_BITALG),
+ BITFIELD (CpuAVX512_BF16),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h
index 2b731c5..19e448a 100644
--- a/opcodes/i386-init.h
+++ b/opcodes/i386-init.h
@@ -24,7 +24,7 @@
0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 0, 1, 1 } }
+ 1, 1, 1, 1, 0, 1, 1 } }
#define CPU_GENERIC32_FLAGS \
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -32,7 +32,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_GENERIC64_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, \
@@ -40,7 +40,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_NONE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -48,7 +48,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I186_FLAGS \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -56,7 +56,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I286_FLAGS \
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -64,7 +64,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I386_FLAGS \
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -72,7 +72,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I486_FLAGS \
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -80,7 +80,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I586_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
@@ -88,7 +88,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_I686_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
@@ -96,7 +96,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PENTIUMPRO_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
@@ -104,7 +104,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, \
@@ -112,7 +112,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P3_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, \
@@ -120,7 +120,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_P4_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, \
@@ -128,7 +128,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_NOCONA_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
@@ -136,7 +136,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CORE_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
@@ -144,7 +144,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CORE2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
@@ -152,7 +152,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_COREI7_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
@@ -160,7 +160,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_K6_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, \
@@ -168,7 +168,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_K6_2_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, \
@@ -176,7 +176,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ATHLON_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, \
@@ -184,7 +184,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_K8_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, \
@@ -192,7 +192,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AMDFAM10_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
@@ -200,7 +200,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BDVER1_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
@@ -208,7 +208,7 @@
0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BDVER2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
@@ -216,7 +216,7 @@
0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, \
0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BDVER3_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
@@ -224,31 +224,31 @@
0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, \
0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BDVER4_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
0, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, \
1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ZNVER1_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
0, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1, \
1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ZNVER2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
0, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1, \
1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
- 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BTVER1_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
@@ -256,7 +256,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BTVER2_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, \
@@ -264,7 +264,7 @@
0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, \
0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_8087_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -272,7 +272,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_287_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
@@ -280,7 +280,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_387_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
@@ -288,7 +288,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_687_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
@@ -296,7 +296,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CMOV_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -304,7 +304,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_FXSR_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -312,7 +312,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CLFLUSH_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -320,7 +320,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_NOP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -328,7 +328,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SYSCALL_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -336,7 +336,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_MMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
@@ -344,7 +344,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
@@ -352,7 +352,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -360,7 +360,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE3_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -368,7 +368,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSSE3_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -376,7 +376,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4_1_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -384,7 +384,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4_2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -392,7 +392,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_VMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -400,7 +400,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -408,7 +408,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_XSAVE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -416,7 +416,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_XSAVEOPT_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -424,7 +424,7 @@
0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AES_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -432,7 +432,7 @@
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PCLMUL_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -440,7 +440,7 @@
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_FMA_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -448,7 +448,7 @@
0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_FMA4_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -456,7 +456,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_XOP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -464,7 +464,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_LWP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -472,7 +472,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BMI_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -480,7 +480,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_TBM_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -488,7 +488,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_MOVBE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -496,7 +496,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CX16_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -504,7 +504,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_RDTSCP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -512,7 +512,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_EPT_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -520,7 +520,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_FSGSBASE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -528,7 +528,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_RDRND_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -536,7 +536,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_F16C_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -544,7 +544,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_BMI2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -552,7 +552,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_LZCNT_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -560,7 +560,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_HLE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -568,7 +568,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_RTM_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -576,7 +576,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_INVPCID_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -584,7 +584,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_VMFUNC_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -592,7 +592,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_3DNOW_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
@@ -600,7 +600,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_3DNOWA_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
@@ -608,7 +608,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PADLOCK_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -616,7 +616,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SVME_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -624,7 +624,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SSE4A_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -632,7 +632,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ABM_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -640,7 +640,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -648,7 +648,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -656,7 +656,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512F_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -664,7 +664,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512CD_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -672,7 +672,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512ER_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -680,7 +680,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512PF_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -688,7 +688,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512DQ_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -696,7 +696,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512BW_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -704,7 +704,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512VL_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -712,7 +712,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512IFMA_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -720,7 +720,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512VBMI_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -728,7 +728,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512_4FMAPS_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -736,7 +736,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512_4VNNIW_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -744,7 +744,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512_VPOPCNTDQ_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -752,7 +752,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512_VBMI2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -760,7 +760,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512_VNNI_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -768,7 +768,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_AVX512_BITALG_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -776,7 +776,15 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
+
+#define CPU_AVX512_BF16_FLAGS \
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
+ 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_L1OM_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
@@ -784,7 +792,7 @@
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 0, 1, 1 } }
+ 1, 1, 1, 1, 0, 1, 1 } }
#define CPU_K1OM_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
@@ -792,7 +800,7 @@
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 0, 1, 1 } }
+ 1, 1, 1, 1, 0, 1, 1 } }
#define CPU_IAMCU_FLAGS \
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -800,7 +808,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ADX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -808,7 +816,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_RDSEED_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -816,7 +824,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PRFCHW_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -824,7 +832,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SMAP_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -832,7 +840,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_MPX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -840,7 +848,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SHA_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -848,7 +856,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CLFLUSHOPT_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -856,7 +864,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_XSAVES_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -864,7 +872,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_XSAVEC_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -872,7 +880,7 @@
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PREFETCHWT1_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -880,7 +888,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SE1_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -888,7 +896,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CLWB_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -896,111 +904,111 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_CLZERO_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_MWAITX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_OSPKE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_RDPID_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PTWRITE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_IBT_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_SHSTK_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_GFNI_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_VAES_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_VPCLMULQDQ_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_WBNOINVD_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_PCONFIG_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_WAITPKG_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 1, 0, 0, 0, 0, 0, 0 } }
#define CPU_CLDEMOTE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1008,7 +1016,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 1, 0, 0, 0, 0, 0 } }
+ 0, 1, 0, 0, 0, 0, 0 } }
#define CPU_MOVDIRI_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1016,7 +1024,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 1, 0, 0, 0, 0 } }
+ 0, 0, 1, 0, 0, 0, 0 } }
#define CPU_MOVDIR64B_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1024,7 +1032,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 1, 0, 0, 0 } }
+ 0, 0, 0, 1, 0, 0, 0 } }
#define CPU_ANY_X87_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
@@ -1032,7 +1040,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_287_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
@@ -1040,7 +1048,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_387_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, \
@@ -1048,7 +1056,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_687_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \
@@ -1056,7 +1064,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_CMOV_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1064,7 +1072,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_FXSR_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1072,7 +1080,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_MMX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
@@ -1080,7 +1088,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_SSE_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
@@ -1088,7 +1096,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_SSE2_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
@@ -1096,7 +1104,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_SSE3_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1104,7 +1112,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_ANY_SSSE3_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1112,7 +1120,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0 } }
+ 0, 0, 0, 0, 0, 0, 0 } }
#define CP[...]
[diff truncated at 100000 bytes]