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[binutils-gdb] RISC-V: Add missing c.unimp instruction.
- From: Jim Wilson <wilson at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 29 Nov 2018 21:11:07 -0000
- Subject: [binutils-gdb] RISC-V: Add missing c.unimp instruction.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=12951a2f080abfd23d0aae0a9a5b2c322fd25c9e
commit 12951a2f080abfd23d0aae0a9a5b2c322fd25c9e
Author: Jim Wilson <jimw@sifive.com>
Date: Thu Nov 29 13:05:25 2018 -0800
RISC-V: Add missing c.unimp instruction.
opcodes/
* riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
(c.unimp): New.
Diff:
---
opcodes/ChangeLog | 5 +++++
opcodes/riscv-opc.c | 3 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4787394..63560f1 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-11-29 Jim Wilson <jimw@sifive.com>
+
+ * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
+ (c.unimp): New.
+
2018-11-27 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (ciw): Fix whitespace to align columns.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index a272e29..3da2a77 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -198,7 +198,7 @@ match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
const struct riscv_opcode riscv_opcodes[] =
{
/* name, xlen, isa, operands, match, mask, match_func, pinfo. */
-{"unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, 0 },
+{"unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, INSN_ALIAS },
{"unimp", 0, {"I", 0}, "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */
{"ebreak", 0, {"C", 0}, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
{"ebreak", 0, {"I", 0}, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 },
@@ -696,6 +696,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"fcvt.q.lu", 64, {"Q", 0}, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
/* Compressed instructions. */
+{"c.unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, 0 },
{"c.ebreak", 0, {"C", 0}, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
{"c.jr", 0, {"C", 0}, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH },
{"c.jalr", 0, {"C", 0}, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR },