This is the mail archive of the
binutils-cvs@sourceware.org
mailing list for the binutils project.
[binutils-gdb] [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension
- From: Sudakshina Das <sudi at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 12 Nov 2018 13:31:35 -0000
- Subject: [binutils-gdb] [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=503ba600259856b41a88b56922e094ea826df270
commit 503ba600259856b41a88b56922e094ea826df270
Author: Sudakshina Das <sudi.das@arm.com>
Date: Mon Nov 12 13:19:12 2018 +0000
[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Bulk Allocation Tag instructions from
MTE. These are the following instructions added in this patch:
- LDGV <Xt>, [<Xn|SP>]!
- STGV <Xt>, [<Xn|SP>]!
This needed a new kind of operand for the new addressing [<Xn|SP>]!
since this has no offset and only takes a pre-indexed version.
Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced.
(AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does
not allow writeback). We also needed new encoding and decoding
functions to be able to do the same.
where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
(aarch64_insn_class): Add ldstgv_indexed.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): New.
* aarch64-asm.h (ins_addr_simple_2): Declare the above.
* aarch64-dis.c (aarch64_ext_addr_simple_2): New.
* aarch64-dis.h (ext_addr_simple_2): Declare the above.
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
(aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
(AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
(warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
Diff:
---
gas/ChangeLog | 10 +
gas/config/tc-aarch64.c | 20 +-
gas/testsuite/gas/aarch64/armv8_5-a-memtag.d | 11 +
gas/testsuite/gas/aarch64/armv8_5-a-memtag.s | 13 +
gas/testsuite/gas/aarch64/illegal-memtag.l | 7 +
gas/testsuite/gas/aarch64/illegal-memtag.s | 12 +
include/ChangeLog | 5 +
include/opcode/aarch64.h | 2 +
opcodes/ChangeLog | 15 +
opcodes/aarch64-asm-2.c | 694 +++----
opcodes/aarch64-asm.c | 11 +
opcodes/aarch64-asm.h | 1 +
opcodes/aarch64-dis-2.c | 2586 +++++++++++++-------------
opcodes/aarch64-dis.c | 17 +
opcodes/aarch64-dis.h | 1 +
opcodes/aarch64-opc-2.c | 31 +-
opcodes/aarch64-opc.c | 6 +
opcodes/aarch64-tbl.h | 4 +
18 files changed, 1801 insertions(+), 1645 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index eead118..eea9a4e 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,15 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
+ * config/tc-aarch64.c (parse_operands): Add switch case for
+ AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
+ (warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldg.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index a5eee96..3fed11c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3372,6 +3372,7 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
[base,Wm,(S|U)XTW {#imm}]
Pre-indexed
[base,#imm]!
+ [base]! // in ld/stgv
Post-indexed
[base],#imm
[base],Xm // in SIMD ld/st structure
@@ -3680,10 +3681,11 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
}
/* If at this point neither .preind nor .postind is set, we have a
- bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
+ bare [Rn]{!}; reject [Rn]! except for ld/stgv but accept [Rn]
+ as a shorthand for [Rn,#0]. */
if (operand->addr.preind == 0 && operand->addr.postind == 0)
{
- if (operand->addr.writeback)
+ if (operand->type != AARCH64_OPND_ADDR_SIMPLE_2 && operand->addr.writeback)
{
/* Reject [Rn]! */
set_syntax_error (_("missing offset in the pre-indexed address"));
@@ -6137,6 +6139,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_ADDR_SIMPLE:
+ case AARCH64_OPND_ADDR_SIMPLE_2:
case AARCH64_OPND_SIMD_ADDR_SIMPLE:
{
/* [<Xn|SP>{, #<simm>}] */
@@ -6146,7 +6149,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
|| !info->addr.preind || info->addr.postind
- || info->addr.writeback)
+ || (info->addr.writeback
+ && operands[i] != AARCH64_OPND_ADDR_SIMPLE_2))
{
set_syntax_error (_("invalid addressing mode"));
goto failure;
@@ -6169,6 +6173,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
}
}
po_char_or_fail (']');
+ if (operands[i] == AARCH64_OPND_ADDR_SIMPLE_2)
+ po_char_or_fail ('!');
break;
}
@@ -6766,6 +6772,14 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
&& opnds[1].addr.writeback)
as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
break;
+
+ case ldstgv_indexed:
+ /* Load operations must load different registers. */
+ if ((opcode->opcode & (1 << 22))
+ && opnds[0].reg.regno == opnds[1].addr.base_regno)
+ as_warn (_("unpredictable load of register -- `%s'"), str);
+ break;
+
case ldstpair_off:
case ldstnapair_offs:
case ldstpair_indexed:
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
index 363bbe2..fa56bfa 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
@@ -121,3 +121,14 @@ Disassembly of section \.text:
.*: d960001f ldg xzr, \[x0\]
.*: d96ff000 ldg x0, \[x0, #4080\]
.*: d9700000 ldg x0, \[x0, #-4096\]
+.*: d9e0001b ldgv x27, \[x0\]!
+.*: d9e00360 ldgv x0, \[x27\]!
+.*: d9e00379 ldgv x25, \[x27\]!
+.*: d9e003e0 ldgv x0, \[sp\]!
+.*: d9e0001f ldgv xzr, \[x0\]!
+.*: d9a00000 stgv x0, \[x0\]!
+.*: d9a0001b stgv x27, \[x0\]!
+.*: d9a00360 stgv x0, \[x27\]!
+.*: d9a00379 stgv x25, \[x27\]!
+.*: d9a003e0 stgv x0, \[sp\]!
+.*: d9a0001f stgv xzr, \[x0\]!
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
index 62c9436..2c2ff8f 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
@@ -30,6 +30,14 @@ func:
\op [sp], #-4096
.endm
+ .macro expand_ldg_bulk op
+ \op x27, [x0]!
+ \op x0, [x27]!
+ \op x25, [x27]!
+ \op x0, [sp]!
+ \op xzr, [x0]!
+ .endm
+
# IRG
expand_3_reg irg
irg sp, x0
@@ -98,3 +106,8 @@ func:
ldg xzr, [x0, #0]
ldg x0, [x0, #4080]
ldg x0, [x0, #-4096]
+
+ expand_ldg_bulk ldgv
+
+ stgv x0, [x0]!
+ expand_ldg_bulk stgv
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index dfdf00a..0d499d9 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -12,6 +12,9 @@
[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
+[^:]*:[0-9]+: Warning: unpredictable load of register -- `ldgv x1,\[x1\]!'
+[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `ldgv x1,\[x2\]'
+[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `stgv x1,\[x2\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
@@ -37,3 +40,7 @@
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgv sp,\[x1\]!'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgv x0,\[xzr\]!'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgv sp,\[x1\]!'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgv x0,\[xzr\]!'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
index 35d1b12..7b7dcd9 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.s
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
@@ -20,6 +20,14 @@ func:
stgp x1, x2, [x3, #33]
stgp x1, x2, [x3, #-1025]
+ # LDGV : Warn for Xt == Xn
+ # STGV : Sould not warn for above
+ ldgv x1, [x1]!
+ stgv x1, [x1]!
+ # Error for no writeback
+ ldgv x1, [x2]
+ stgv x1, [x2]
+
# Illegal SP/XZR registers
irg xzr, x2, x3
irg x1, xzr, x3
@@ -46,3 +54,7 @@ func:
stgp x0, x0, [xzr]
ldg sp, [x0, #16]
ldg x0, [xzr, #16]
+ ldgv sp, [x1]!
+ ldgv x0, [xzr]!
+ stgv sp, [x1]!
+ stgv x0, [xzr]!
diff --git a/include/ChangeLog b/include/ChangeLog
index 491bbd4..d23816f 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
+ * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
+ (aarch64_insn_class): Add ldstgv_indexed.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
and AARCH64_OPND_ADDR_SIMM13.
(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c4c573a..0840239 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -275,6 +275,7 @@ enum aarch64_opnd
AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
+ AARCH64_OPND_ADDR_SIMPLE_2, /* Address of ld/stgv. */
AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
@@ -561,6 +562,7 @@ enum aarch64_insn_class
ldstnapair_offs,
ldstpair_off,
ldstpair_indexed,
+ ldstgv_indexed,
loadlit,
log_imm,
log_shift,
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b652efd..0b5daa9 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,20 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
+ * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
+ * aarch64-asm.h (ins_addr_simple_2): Declare the above.
+ * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
+ * aarch64-dis.h (ext_addr_simple_2): Declare the above.
+ * aarch64-opc.c (operand_general_constraint_met_p): Add case for
+ AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
+ (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
+ * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
+ (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
* aarch64-tbl.h (QL_LDG): New.
(aarch64_opcode_table): Add ldg.
* aarch64-asm-2.c: Regenerated.
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index ed1d91d..afa16db 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -201,390 +201,390 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 757: /* extr */
value = 757; /* --> extr. */
break;
- case 988: /* bic */
- case 987: /* and */
- value = 987; /* --> and. */
- break;
- case 990: /* mov */
- case 989: /* orr */
- value = 989; /* --> orr. */
- break;
- case 993: /* tst */
- case 992: /* ands */
- value = 992; /* --> ands. */
- break;
- case 998: /* uxtw */
- case 997: /* mov */
- case 996: /* orr */
- value = 996; /* --> orr. */
+ case 990: /* bic */
+ case 989: /* and */
+ value = 989; /* --> and. */
+ break;
+ case 992: /* mov */
+ case 991: /* orr */
+ value = 991; /* --> orr. */
+ break;
+ case 995: /* tst */
+ case 994: /* ands */
+ value = 994; /* --> ands. */
+ break;
+ case 1000: /* uxtw */
+ case 999: /* mov */
+ case 998: /* orr */
+ value = 998; /* --> orr. */
break;
- case 1000: /* mvn */
- case 999: /* orn */
- value = 999; /* --> orn. */
+ case 1002: /* mvn */
+ case 1001: /* orn */
+ value = 1001; /* --> orn. */
break;
- case 1004: /* tst */
- case 1003: /* ands */
- value = 1003; /* --> ands. */
+ case 1006: /* tst */
+ case 1005: /* ands */
+ value = 1005; /* --> ands. */
break;
- case 1130: /* staddb */
- case 1034: /* ldaddb */
- value = 1034; /* --> ldaddb. */
+ case 1132: /* staddb */
+ case 1036: /* ldaddb */
+ value = 1036; /* --> ldaddb. */
break;
- case 1131: /* staddh */
- case 1035: /* ldaddh */
- value = 1035; /* --> ldaddh. */
+ case 1133: /* staddh */
+ case 1037: /* ldaddh */
+ value = 1037; /* --> ldaddh. */
break;
- case 1132: /* stadd */
- case 1036: /* ldadd */
- value = 1036; /* --> ldadd. */
+ case 1134: /* stadd */
+ case 1038: /* ldadd */
+ value = 1038; /* --> ldadd. */
break;
- case 1133: /* staddlb */
- case 1038: /* ldaddlb */
- value = 1038; /* --> ldaddlb. */
+ case 1135: /* staddlb */
+ case 1040: /* ldaddlb */
+ value = 1040; /* --> ldaddlb. */
break;
- case 1134: /* staddlh */
- case 1041: /* ldaddlh */
- value = 1041; /* --> ldaddlh. */
+ case 1136: /* staddlh */
+ case 1043: /* ldaddlh */
+ value = 1043; /* --> ldaddlh. */
break;
- case 1135: /* staddl */
- case 1044: /* ldaddl */
- value = 1044; /* --> ldaddl. */
+ case 1137: /* staddl */
+ case 1046: /* ldaddl */
+ value = 1046; /* --> ldaddl. */
break;
- case 1136: /* stclrb */
- case 1046: /* ldclrb */
- value = 1046; /* --> ldclrb. */
+ case 1138: /* stclrb */
+ case 1048: /* ldclrb */
+ value = 1048; /* --> ldclrb. */
break;
- case 1137: /* stclrh */
- case 1047: /* ldclrh */
- value = 1047; /* --> ldclrh. */
+ case 1139: /* stclrh */
+ case 1049: /* ldclrh */
+ value = 1049; /* --> ldclrh. */
break;
- case 1138: /* stclr */
- case 1048: /* ldclr */
- value = 1048; /* --> ldclr. */
+ case 1140: /* stclr */
+ case 1050: /* ldclr */
+ value = 1050; /* --> ldclr. */
break;
- case 1139: /* stclrlb */
- case 1050: /* ldclrlb */
- value = 1050; /* --> ldclrlb. */
+ case 1141: /* stclrlb */
+ case 1052: /* ldclrlb */
+ value = 1052; /* --> ldclrlb. */
break;
- case 1140: /* stclrlh */
- case 1053: /* ldclrlh */
- value = 1053; /* --> ldclrlh. */
+ case 1142: /* stclrlh */
+ case 1055: /* ldclrlh */
+ value = 1055; /* --> ldclrlh. */
break;
- case 1141: /* stclrl */
- case 1056: /* ldclrl */
- value = 1056; /* --> ldclrl. */
+ case 1143: /* stclrl */
+ case 1058: /* ldclrl */
+ value = 1058; /* --> ldclrl. */
break;
- case 1142: /* steorb */
- case 1058: /* ldeorb */
- value = 1058; /* --> ldeorb. */
+ case 1144: /* steorb */
+ case 1060: /* ldeorb */
+ value = 1060; /* --> ldeorb. */
break;
- case 1143: /* steorh */
- case 1059: /* ldeorh */
- value = 1059; /* --> ldeorh. */
+ case 1145: /* steorh */
+ case 1061: /* ldeorh */
+ value = 1061; /* --> ldeorh. */
break;
- case 1144: /* steor */
- case 1060: /* ldeor */
- value = 1060; /* --> ldeor. */
+ case 1146: /* steor */
+ case 1062: /* ldeor */
+ value = 1062; /* --> ldeor. */
break;
- case 1145: /* steorlb */
- case 1062: /* ldeorlb */
- value = 1062; /* --> ldeorlb. */
+ case 1147: /* steorlb */
+ case 1064: /* ldeorlb */
+ value = 1064; /* --> ldeorlb. */
break;
- case 1146: /* steorlh */
- case 1065: /* ldeorlh */
- value = 1065; /* --> ldeorlh. */
+ case 1148: /* steorlh */
+ case 1067: /* ldeorlh */
+ value = 1067; /* --> ldeorlh. */
break;
- case 1147: /* steorl */
- case 1068: /* ldeorl */
- value = 1068; /* --> ldeorl. */
+ case 1149: /* steorl */
+ case 1070: /* ldeorl */
+ value = 1070; /* --> ldeorl. */
break;
- case 1148: /* stsetb */
- case 1070: /* ldsetb */
- value = 1070; /* --> ldsetb. */
+ case 1150: /* stsetb */
+ case 1072: /* ldsetb */
+ value = 1072; /* --> ldsetb. */
break;
- case 1149: /* stseth */
- case 1071: /* ldseth */
- value = 1071; /* --> ldseth. */
+ case 1151: /* stseth */
+ case 1073: /* ldseth */
+ value = 1073; /* --> ldseth. */
break;
- case 1150: /* stset */
- case 1072: /* ldset */
- value = 1072; /* --> ldset. */
+ case 1152: /* stset */
+ case 1074: /* ldset */
+ value = 1074; /* --> ldset. */
break;
- case 1151: /* stsetlb */
- case 1074: /* ldsetlb */
- value = 1074; /* --> ldsetlb. */
+ case 1153: /* stsetlb */
+ case 1076: /* ldsetlb */
+ value = 1076; /* --> ldsetlb. */
break;
- case 1152: /* stsetlh */
- case 1077: /* ldsetlh */
- value = 1077; /* --> ldsetlh. */
+ case 1154: /* stsetlh */
+ case 1079: /* ldsetlh */
+ value = 1079; /* --> ldsetlh. */
break;
- case 1153: /* stsetl */
- case 1080: /* ldsetl */
- value = 1080; /* --> ldsetl. */
+ case 1155: /* stsetl */
+ case 1082: /* ldsetl */
+ value = 1082; /* --> ldsetl. */
break;
- case 1154: /* stsmaxb */
- case 1082: /* ldsmaxb */
- value = 1082; /* --> ldsmaxb. */
+ case 1156: /* stsmaxb */
+ case 1084: /* ldsmaxb */
+ value = 1084; /* --> ldsmaxb. */
break;
- case 1155: /* stsmaxh */
- case 1083: /* ldsmaxh */
- value = 1083; /* --> ldsmaxh. */
+ case 1157: /* stsmaxh */
+ case 1085: /* ldsmaxh */
+ value = 1085; /* --> ldsmaxh. */
break;
- case 1156: /* stsmax */
- case 1084: /* ldsmax */
- value = 1084; /* --> ldsmax. */
+ case 1158: /* stsmax */
+ case 1086: /* ldsmax */
+ value = 1086; /* --> ldsmax. */
break;
- case 1157: /* stsmaxlb */
- case 1086: /* ldsmaxlb */
- value = 1086; /* --> ldsmaxlb. */
+ case 1159: /* stsmaxlb */
+ case 1088: /* ldsmaxlb */
+ value = 1088; /* --> ldsmaxlb. */
break;
- case 1158: /* stsmaxlh */
- case 1089: /* ldsmaxlh */
- value = 1089; /* --> ldsmaxlh. */
+ case 1160: /* stsmaxlh */
+ case 1091: /* ldsmaxlh */
+ value = 1091; /* --> ldsmaxlh. */
break;
- case 1159: /* stsmaxl */
- case 1092: /* ldsmaxl */
- value = 1092; /* --> ldsmaxl. */
+ case 1161: /* stsmaxl */
+ case 1094: /* ldsmaxl */
+ value = 1094; /* --> ldsmaxl. */
break;
- case 1160: /* stsminb */
- case 1094: /* ldsminb */
- value = 1094; /* --> ldsminb. */
+ case 1162: /* stsminb */
+ case 1096: /* ldsminb */
+ value = 1096; /* --> ldsminb. */
break;
- case 1161: /* stsminh */
- case 1095: /* ldsminh */
- value = 1095; /* --> ldsminh. */
+ case 1163: /* stsminh */
+ case 1097: /* ldsminh */
+ value = 1097; /* --> ldsminh. */
break;
- case 1162: /* stsmin */
- case 1096: /* ldsmin */
- value = 1096; /* --> ldsmin. */
+ case 1164: /* stsmin */
+ case 1098: /* ldsmin */
+ value = 1098; /* --> ldsmin. */
break;
- case 1163: /* stsminlb */
- case 1098: /* ldsminlb */
- value = 1098; /* --> ldsminlb. */
+ case 1165: /* stsminlb */
+ case 1100: /* ldsminlb */
+ value = 1100; /* --> ldsminlb. */
break;
- case 1164: /* stsminlh */
- case 1101: /* ldsminlh */
- value = 1101; /* --> ldsminlh. */
+ case 1166: /* stsminlh */
+ case 1103: /* ldsminlh */
+ value = 1103; /* --> ldsminlh. */
break;
- case 1165: /* stsminl */
- case 1104: /* ldsminl */
- value = 1104; /* --> ldsminl. */
+ case 1167: /* stsminl */
+ case 1106: /* ldsminl */
+ value = 1106; /* --> ldsminl. */
break;
- case 1166: /* stumaxb */
- case 1106: /* ldumaxb */
- value = 1106; /* --> ldumaxb. */
+ case 1168: /* stumaxb */
+ case 1108: /* ldumaxb */
+ value = 1108; /* --> ldumaxb. */
break;
- case 1167: /* stumaxh */
- case 1107: /* ldumaxh */
- value = 1107; /* --> ldumaxh. */
+ case 1169: /* stumaxh */
+ case 1109: /* ldumaxh */
+ value = 1109; /* --> ldumaxh. */
break;
- case 1168: /* stumax */
- case 1108: /* ldumax */
- value = 1108; /* --> ldumax. */
+ case 1170: /* stumax */
+ case 1110: /* ldumax */
+ value = 1110; /* --> ldumax. */
break;
- case 1169: /* stumaxlb */
- case 1110: /* ldumaxlb */
- value = 1110; /* --> ldumaxlb. */
+ case 1171: /* stumaxlb */
+ case 1112: /* ldumaxlb */
+ value = 1112; /* --> ldumaxlb. */
break;
- case 1170: /* stumaxlh */
- case 1113: /* ldumaxlh */
- value = 1113; /* --> ldumaxlh. */
+ case 1172: /* stumaxlh */
+ case 1115: /* ldumaxlh */
+ value = 1115; /* --> ldumaxlh. */
break;
- case 1171: /* stumaxl */
- case 1116: /* ldumaxl */
- value = 1116; /* --> ldumaxl. */
+ case 1173: /* stumaxl */
+ case 1118: /* ldumaxl */
+ value = 1118; /* --> ldumaxl. */
break;
- case 1172: /* stuminb */
- case 1118: /* lduminb */
- value = 1118; /* --> lduminb. */
+ case 1174: /* stuminb */
+ case 1120: /* lduminb */
+ value = 1120; /* --> lduminb. */
break;
- case 1173: /* stuminh */
- case 1119: /* lduminh */
- value = 1119; /* --> lduminh. */
+ case 1175: /* stuminh */
+ case 1121: /* lduminh */
+ value = 1121; /* --> lduminh. */
break;
- case 1174: /* stumin */
- case 1120: /* ldumin */
- value = 1120; /* --> ldumin. */
+ case 1176: /* stumin */
+ case 1122: /* ldumin */
+ value = 1122; /* --> ldumin. */
break;
- case 1175: /* stuminlb */
- case 1122: /* lduminlb */
- value = 1122; /* --> lduminlb. */
+ case 1177: /* stuminlb */
+ case 1124: /* lduminlb */
+ value = 1124; /* --> lduminlb. */
break;
- case 1176: /* stuminlh */
- case 1125: /* lduminlh */
- value = 1125; /* --> lduminlh. */
+ case 1178: /* stuminlh */
+ case 1127: /* lduminlh */
+ value = 1127; /* --> lduminlh. */
break;
- case 1177: /* stuminl */
- case 1128: /* lduminl */
- value = 1128; /* --> lduminl. */
- break;
- case 1179: /* mov */
- case 1178: /* movn */
- value = 1178; /* --> movn. */
+ case 1179: /* stuminl */
+ case 1130: /* lduminl */
+ value = 1130; /* --> lduminl. */
break;
case 1181: /* mov */
- case 1180: /* movz */
- value = 1180; /* --> movz. */
- break;
- case 1227: /* autibsp */
- case 1226: /* autibz */
- case 1225: /* autiasp */
- case 1224: /* autiaz */
- case 1223: /* pacibsp */
- case 1222: /* pacibz */
- case 1221: /* paciasp */
- case 1220: /* paciaz */
- case 1201: /* psb */
- case 1200: /* esb */
- case 1199: /* autib1716 */
- case 1198: /* autia1716 */
- case 1197: /* pacib1716 */
- case 1196: /* pacia1716 */
- case 1195: /* xpaclri */
- case 1194: /* sevl */
- case 1193: /* sev */
- case 1192: /* wfi */
- case 1191: /* wfe */
- case 1190: /* yield */
- case 1189: /* bti */
- case 1188: /* csdb */
- case 1187: /* nop */
- case 1186: /* hint */
- value = 1186; /* --> hint. */
- break;
- case 1205: /* pssbb */
- case 1204: /* ssbb */
- case 1203: /* dsb */
- value = 1203; /* --> dsb. */
- break;
- case 1216: /* cpp */
- case 1215: /* dvp */
- case 1214: /* cfp */
- case 1213: /* tlbi */
- case 1212: /* ic */
- case 1211: /* dc */
- case 1210: /* at */
- case 1209: /* sys */
- value = 1209; /* --> sys. */
- break;
- case 2025: /* bic */
- case 1275: /* and */
- value = 1275; /* --> and. */
- break;
- case 1258: /* mov */
+ case 1180: /* movn */
+ value = 1180; /* --> movn. */
+ break;
+ case 1183: /* mov */
+ case 1182: /* movz */
+ value = 1182; /* --> movz. */
+ break;
+ case 1229: /* autibsp */
+ case 1228: /* autibz */
+ case 1227: /* autiasp */
+ case 1226: /* autiaz */
+ case 1225: /* pacibsp */
+ case 1224: /* pacibz */
+ case 1223: /* paciasp */
+ case 1222: /* paciaz */
+ case 1203: /* psb */
+ case 1202: /* esb */
+ case 1201: /* autib1716 */
+ case 1200: /* autia1716 */
+ case 1199: /* pacib1716 */
+ case 1198: /* pacia1716 */
+ case 1197: /* xpaclri */
+ case 1196: /* sevl */
+ case 1195: /* sev */
+ case 1194: /* wfi */
+ case 1193: /* wfe */
+ case 1192: /* yield */
+ case 1191: /* bti */
+ case 1190: /* csdb */
+ case 1189: /* nop */
+ case 1188: /* hint */
+ value = 1188; /* --> hint. */
+ break;
+ case 1207: /* pssbb */
+ case 1206: /* ssbb */
+ case 1205: /* dsb */
+ value = 1205; /* --> dsb. */
+ break;
+ case 1218: /* cpp */
+ case 1217: /* dvp */
+ case 1216: /* cfp */
+ case 1215: /* tlbi */
+ case 1214: /* ic */
+ case 1213: /* dc */
+ case 1212: /* at */
+ case 1211: /* sys */
+ value = 1211; /* --> sys. */
+ break;
+ case 2027: /* bic */
case 1277: /* and */
value = 1277; /* --> and. */
break;
- case 1262: /* movs */
- case 1278: /* ands */
- value = 1278; /* --> ands. */
+ case 1260: /* mov */
+ case 1279: /* and */
+ value = 1279; /* --> and. */
break;
- case 2026: /* cmple */
- case 1313: /* cmpge */
- value = 1313; /* --> cmpge. */
+ case 1264: /* movs */
+ case 1280: /* ands */
+ value = 1280; /* --> ands. */
break;
- case 2029: /* cmplt */
- case 1316: /* cmpgt */
- value = 1316; /* --> cmpgt. */
+ case 2028: /* cmple */
+ case 1315: /* cmpge */
+ value = 1315; /* --> cmpge. */
break;
- case 2027: /* cmplo */
- case 1318: /* cmphi */
- value = 1318; /* --> cmphi. */
+ case 2031: /* cmplt */
+ case 1318: /* cmpgt */
+ value = 1318; /* --> cmpgt. */
break;
- case 2028: /* cmpls */
- case 1321: /* cmphs */
- value = 1321; /* --> cmphs. */
+ case 2029: /* cmplo */
+ case 1320: /* cmphi */
+ value = 1320; /* --> cmphi. */
break;
- case 1255: /* mov */
- case 1343: /* cpy */
- value = 1343; /* --> cpy. */
+ case 2030: /* cmpls */
+ case 1323: /* cmphs */
+ value = 1323; /* --> cmphs. */
break;
case 1257: /* mov */
- case 1344: /* cpy */
- value = 1344; /* --> cpy. */
- break;
- case 2036: /* fmov */
- case 1260: /* mov */
case 1345: /* cpy */
value = 1345; /* --> cpy. */
break;
- case 1250: /* mov */
- case 1357: /* dup */
- value = 1357; /* --> dup. */
+ case 1259: /* mov */
+ case 1346: /* cpy */
+ value = 1346; /* --> cpy. */
break;
- case 1252: /* mov */
- case 1249: /* mov */
- case 1358: /* dup */
- value = 1358; /* --> dup. */
+ case 2038: /* fmov */
+ case 1262: /* mov */
+ case 1347: /* cpy */
+ value = 1347; /* --> cpy. */
break;
- case 2035: /* fmov */
- case 1254: /* mov */
+ case 1252: /* mov */
case 1359: /* dup */
value = 1359; /* --> dup. */
break;
- case 1253: /* mov */
- case 1360: /* dupm */
- value = 1360; /* --> dupm. */
+ case 1254: /* mov */
+ case 1251: /* mov */
+ case 1360: /* dup */
+ value = 1360; /* --> dup. */
+ break;
+ case 2037: /* fmov */
+ case 1256: /* mov */
+ case 1361: /* dup */
+ value = 1361; /* --> dup. */
break;
- case 2030: /* eon */
- case 1362: /* eor */
- value = 1362; /* --> eor. */
+ case 1255: /* mov */
+ case 1362: /* dupm */
+ value = 1362; /* --> dupm. */
break;
- case 1263: /* not */
+ case 2032: /* eon */
case 1364: /* eor */
value = 1364; /* --> eor. */
break;
- case 1264: /* nots */
- case 1365: /* eors */
- value = 1365; /* --> eors. */
+ case 1265: /* not */
+ case 1366: /* eor */
+ value = 1366; /* --> eor. */
break;
- case 2031: /* facle */
- case 1370: /* facge */
- value = 1370; /* --> facge. */
+ case 1266: /* nots */
+ case 1367: /* eors */
+ value = 1367; /* --> eors. */
break;
- case 2032: /* faclt */
- case 1371: /* facgt */
- value = 1371; /* --> facgt. */
+ case 2033: /* facle */
+ case 1372: /* facge */
+ value = 1372; /* --> facge. */
break;
- case 2033: /* fcmle */
- case 1384: /* fcmge */
- value = 1384; /* --> fcmge. */
+ case 2034: /* faclt */
+ case 1373: /* facgt */
+ value = 1373; /* --> facgt. */
break;
- case 2034: /* fcmlt */
- case 1386: /* fcmgt */
- value = 1386; /* --> fcmgt. */
+ case 2035: /* fcmle */
+ case 1386: /* fcmge */
+ value = 1386; /* --> fcmge. */
break;
- case 1247: /* fmov */
- case 1392: /* fcpy */
- value = 1392; /* --> fcpy. */
+ case 2036: /* fcmlt */
+ case 1388: /* fcmgt */
+ value = 1388; /* --> fcmgt. */
break;
- case 1246: /* fmov */
- case 1415: /* fdup */
- value = 1415; /* --> fdup. */
+ case 1249: /* fmov */
+ case 1394: /* fcpy */
+ value = 1394; /* --> fcpy. */
break;
- case 1248: /* mov */
- case 1746: /* orr */
- value = 1746; /* --> orr. */
+ case 1248: /* fmov */
+ case 1417: /* fdup */
+ value = 1417; /* --> fdup. */
break;
- case 2037: /* orn */
- case 1747: /* orr */
- value = 1747; /* --> orr. */
+ case 1250: /* mov */
+ case 1748: /* orr */
+ value = 1748; /* --> orr. */
break;
- case 1251: /* mov */
+ case 2039: /* orn */
case 1749: /* orr */
value = 1749; /* --> orr. */
break;
- case 1261: /* movs */
- case 1750: /* orrs */
- value = 1750; /* --> orrs. */
+ case 1253: /* mov */
+ case 1751: /* orr */
+ value = 1751; /* --> orr. */
break;
- case 1256: /* mov */
- case 1812: /* sel */
- value = 1812; /* --> sel. */
+ case 1263: /* movs */
+ case 1752: /* orrs */
+ value = 1752; /* --> orrs. */
break;
- case 1259: /* mov */
- case 1813: /* sel */
- value = 1813; /* --> sel. */
+ case 1258: /* mov */
+ case 1814: /* sel */
+ value = 1814; /* --> sel. */
+ break;
+ case 1261: /* mov */
+ case 1815: /* sel */
+ value = 1815; /* --> sel. */
break;
default: return NULL;
}
@@ -627,7 +627,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 27:
case 28:
case 29:
- case 159:
case 160:
case 161:
case 162:
@@ -637,7 +636,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 166:
case 167:
case 168:
- case 181:
+ case 169:
case 182:
case 183:
case 184:
@@ -646,8 +645,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 187:
case 188:
case 189:
- case 193:
- case 196:
+ case 190:
+ case 194:
+ case 197:
return aarch64_ins_regno (self, info, code, inst, errors);
case 13:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -659,7 +659,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 31:
case 32:
case 33:
- case 198:
+ case 199:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 34:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -693,9 +693,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 79:
case 80:
case 81:
- case 156:
- case 158:
- case 173:
+ case 157:
+ case 159:
case 174:
case 175:
case 176:
@@ -703,6 +702,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 178:
case 179:
case 180:
+ case 181:
return aarch64_ins_imm (self, info, code, inst, errors);
case 42:
case 43:
@@ -712,10 +712,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 46:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 50:
- case 147:
+ case 148:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 67:
- case 154:
+ case 155:
return aarch64_ins_limm (self, info, code, inst, errors);
case 68:
return aarch64_ins_aimm (self, info, code, inst, errors);
@@ -725,68 +725,69 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors);
case 72:
case 73:
- case 152:
+ case 153:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 74:
- case 151:
+ case 152:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 75:
case 76:
return aarch64_ins_cond (self, info, code, inst, errors);
case 82:
- case 91:
+ case 92:
return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 83:
- return aarch64_ins_addr_regoff (self, info, code, inst, errors);
+ return aarch64_ins_addr_simple_2 (self, info, code, inst, errors);
case 84:
+ return aarch64_ins_addr_regoff (self, info, code, inst, errors);
case 85:
case 86:
- case 88:
- case 90:
- return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 87:
- return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
case 89:
+ case 91:
+ return aarch64_ins_addr_simm (self, info, code, inst, errors);
+ case 88:
+ return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
+ case 90:
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
- case 92:
- return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 93:
- return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
+ return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 94:
- return aarch64_ins_sysreg (self, info, code, inst, errors);
+ return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
case 95:
- return aarch64_ins_pstatefield (self, info, code, inst, errors);
+ return aarch64_ins_sysreg (self, info, code, inst, errors);
case 96:
+ return aarch64_ins_pstatefield (self, info, code, inst, errors);
case 97:
case 98:
case 99:
case 100:
- return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 101:
+ return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 102:
- return aarch64_ins_barrier (self, info, code, inst, errors);
case 103:
- return aarch64_ins_prfop (self, info, code, inst, errors);
+ return aarch64_ins_barrier (self, info, code, inst, errors);
case 104:
+ return aarch64_ins_prfop (self, info, code, inst, errors);
case 105:
- return aarch64_ins_hint (self, info, code, inst, errors);
case 106:
- return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
+ return aarch64_ins_hint (self, info, code, inst, errors);
case 107:
+ return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 108:
case 109:
case 110:
- return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 111:
- return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 112:
- return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 113:
+ return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 114:
case 115:
case 116:
- return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 117:
+ return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 118:
case 119:
case 120:
@@ -799,8 +800,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 127:
case 128:
case 129:
- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 130:
+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 131:
case 132:
case 133:
@@ -808,48 +809,49 @@ aarch64_insert_operand (const aarch64_operand *self,
case 135:
case 136:
case 137:
- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 138:
+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 139:
case 140:
case 141:
- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 142:
- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 143:
- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 144:
- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 145:
- return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 146:
+ return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ case 147:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
- case 148:
- return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 149:
- return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 150:
+ return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ case 151:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 153:
+ case 154:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 155:
+ case 156:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 157:
+ case 158:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 169:
case 170:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 171:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 172:
+ case 173:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 190:
case 191:
case 192:
+ case 193:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 194:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 195:
- case 197:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 196:
+ case 198:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index e53b98a..e3380cb 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -618,6 +618,17 @@ aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE;
}
+/* Encode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
+bfd_boolean
+aarch64_ins_addr_simple_2 (const aarch64_operand *self,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst,
+ aarch64_operand_error *errors)
+
+{
+ return aarch64_ins_addr_simple (self, info, code, inst, errors);
+}
+
/* Encode the address operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
bfd_boolean
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index 0524f91..fec5448 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -59,6 +59,7 @@ AARCH64_DECL_OPD_INSERTER (ins_limm);
AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
AARCH64_DECL_OPD_INSERTER (ins_ft);
AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
+AARCH64_DECL_OPD_INSERTER (ins_addr_simple_2);
AARCH64_DECL_OPD_INSERTER (ins_addr_offset);
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index faead8e..65c48ee 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -40,7 +40,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0xxx0000xxxxxxxxxxxxxxxxxxxxxxxx
adr. */
- return 1183;
+ return 1185;
}
else
{
@@ -48,7 +48,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1xxx0000xxxxxxxxxxxxxxxxxxxxxxxx
adrp. */
- return 1184;
+ return 1186;
}
}
else
@@ -143,7 +143,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x00100x001xxxxx0xxxxxxxxxxxxxxx
casp. */
- return 1018;
+ return 1020;
}
else
{
@@ -195,7 +195,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x00100x001xxxxx1xxxxxxxxxxxxxxx
caspl. */
- return 1020;
+ return 1022;
}
else
{
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010100x00xxxxxxxxxxxxxxxxxxxxxx
stnp. */
- return 967;
+ return 969;
}
else
{
@@ -224,7 +224,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110100x00xxxxxxxxxxxxxxxxxxxxxx
stgp. */
- return 976;
+ return 978;
}
}
}
@@ -242,7 +242,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x00100x100xxxxx0xxxxxxxxxxxxxxx
stllrb. */
- return 965;
+ return 967;
}
else
{
@@ -250,7 +250,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x100xxxxx0xxxxxxxxxxxxxxx
stllr. */
- return 964;
+ return 966;
}
}
else
@@ -263,7 +263,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x101xxxxx0xxxxxxxxxxxxxxx
casb. */
- return 1006;
+ return 1008;
}
else
{
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x101xxxxx0xxxxxxxxxxxxxxx
cash. */
- return 1007;
+ return 1009;
}
}
else
@@ -280,7 +280,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x101xxxxx0xxxxxxxxxxxxxxx
cas. */
- return 1008;
+ return 1010;
}
}
}
@@ -326,7 +326,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x101xxxxx1xxxxxxxxxxxxxxx
caslb. */
- return 1010;
+ return 1012;
}
else
{
@@ -334,7 +334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x101xxxxx1xxxxxxxxxxxxxxx
caslh. */
- return 1013;
+ return 1015;
}
}
else
@@ -343,7 +343,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x101xxxxx1xxxxxxxxxxxxxxx
casl. */
- return 1016;
+ return 1018;
}
}
}
@@ -356,7 +356,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010100x10xxxxxxxxxxxxxxxxxxxxxx
stp. */
- return 977;
+ return 979;
}
else
{
@@ -364,7 +364,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110100x10xxxxxxxxxxxxxxxxxxxxxx
stgp. */
- return 982;
+ return 984;
}
}
}
@@ -415,7 +415,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x00100x011xxxxx0xxxxxxxxxxxxxxx
caspa. */
- return 1019;
+ return 1021;
}
else
{
@@ -467,7 +467,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x00100x011xxxxx1xxxxxxxxxxxxxxx
caspal. */
- return 1021;
+ return 1023;
}
else
{
@@ -488,7 +488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010100x01xxxxxxxxxxxxxxxxxxxxxx
ldnp. */
- return 968;
+ return 970;
}
else
{
@@ -496,7 +496,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110100x01xxxxxxxxxxxxxxxxxxxxxx
ldpsw. */
- return 975;
+ return 977;
}
}
}
@@ -516,7 +516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x110xxxxx0xxxxxxxxxxxxxxx
ldlarb. */
- return 962;
+ return 964;
}
else
{
@@ -524,7 +524,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x110xxxxx0xxxxxxxxxxxxxxx
ldlarh. */
- return 963;
+ return 965;
}
}
else
@@ -533,7 +533,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x110xxxxx0xxxxxxxxxxxxxxx
ldlar. */
- return 961;
+ return 963;
}
}
else
@@ -546,7 +546,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x111xxxxx0xxxxxxxxxxxxxxx
casab. */
- return 1009;
+ return 1011;
}
else
{
@@ -554,7 +554,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x111xxxxx0xxxxxxxxxxxxxxx
casah. */
- return 1012;
+ return 1014;
}
}
else
@@ -563,7 +563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x111xxxxx0xxxxxxxxxxxxxxx
casa. */
- return 1015;
+ return 1017;
}
}
}
@@ -609,7 +609,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0000100x111xxxxx1xxxxxxxxxxxxxxx
casalb. */
- return 1011;
+ return 1013;
}
else
{
@@ -617,7 +617,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0100100x111xxxxx1xxxxxxxxxxxxxxx
casalh. */
- return 1014;
+ return 1016;
}
}
else
@@ -626,7 +626,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x00100x111xxxxx1xxxxxxxxxxxxxxx
casal. */
- return 1017;
+ return 1019;
}
}
}
@@ -639,7 +639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010100x11xxxxxxxxxxxxxxxxxxxxxx
ldp. */
- return 978;
+ return 980;
}
else
{
@@ -647,7 +647,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110100x11xxxxxxxxxxxxxxxxxxxxxx
ldpsw. */
- return 981;
+ return 983;
}
}
}
@@ -665,7 +665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x011000xxxxxxxxxxxxxxxxxxxxxxxx
ldr. */
- return 983;
+ return 985;
}
else
{
@@ -675,7 +675,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
10011000xxxxxxxxxxxxxxxxxxxxxxxx
ldrsw. */
- return 985;
+ return 987;
}
else
{
@@ -683,7 +683,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
11011000xxxxxxxxxxxxxxxxxxxxxxxx
prfm. */
- return 986;
+ return 988;
}
}
}
@@ -822,7 +822,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000001xxxxx000000xxxxxxxxxx
ldaddb. */
- return 1034;
+ return 1036;
}
else
{
@@ -830,7 +830,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000001xxxxx000000xxxxxxxxxx
ldaddh. */
- return 1035;
+ return 1037;
}
}
else
@@ -839,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000001xxxxx000000xxxxxxxxxx
ldadd. */
- return 1036;
+ return 1038;
}
}
else
@@ -852,7 +852,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000101xxxxx000000xxxxxxxxxx
ldaddab. */
- return 1037;
+ return 1039;
}
else
{
@@ -860,7 +860,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000101xxxxx000000xxxxxxxxxx
ldaddah. */
- return 1040;
+ return 1042;
}
}
else
@@ -869,7 +869,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000101xxxxx000000xxxxxxxxxx
ldadda. */
- return 1043;
+ return 1045;
}
}
}
@@ -885,7 +885,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000011xxxxx000000xxxxxxxxxx
ldaddlb. */
- return 1038;
+ return 1040;
}
else
{
@@ -893,7 +893,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000011xxxxx000000xxxxxxxxxx
ldaddlh. */
- return 1041;
+ return 1043;
}
}
else
@@ -902,7 +902,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000011xxxxx000000xxxxxxxxxx
ldaddl. */
- return 1044;
+ return 1046;
}
}
else
@@ -915,7 +915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000111xxxxx000000xxxxxxxxxx
ldaddalb. */
- return 1039;
+ return 1041;
}
else
{
@@ -923,7 +923,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000111xxxxx000000xxxxxxxxxx
ldaddalh. */
- return 1042;
+ return 1044;
}
}
else
@@ -932,7 +932,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000111xxxxx000000xxxxxxxxxx
ldaddal. */
- return 1045;
+ return 1047;
}
}
}
@@ -951,7 +951,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000001xxxxx100000xxxxxxxxxx
swpb. */
- return 1022;
+ return 1024;
}
else
{
@@ -959,7 +959,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000001xxxxx100000xxxxxxxxxx
swph. */
- return 1023;
+ return 1025;
}
}
else
@@ -968,7 +968,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000001xxxxx100000xxxxxxxxxx
swp. */
- return 1024;
+ return 1026;
}
}
else
@@ -981,7 +981,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000101xxxxx100000xxxxxxxxxx
swpab. */
- return 1025;
+ return 1027;
}
else
{
@@ -989,7 +989,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000101xxxxx100000xxxxxxxxxx
swpah. */
- return 1028;
+ return 1030;
}
}
else
@@ -998,7 +998,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000101xxxxx100000xxxxxxxxxx
swpa. */
- return 1031;
+ return 1033;
}
}
}
@@ -1014,7 +1014,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000011xxxxx100000xxxxxxxxxx
swplb. */
- return 1026;
+ return 1028;
}
else
{
@@ -1022,7 +1022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000011xxxxx100000xxxxxxxxxx
swplh. */
- return 1029;
+ return 1031;
}
}
else
@@ -1031,7 +1031,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000011xxxxx100000xxxxxxxxxx
swpl. */
- return 1032;
+ return 1034;
}
}
else
@@ -1044,7 +1044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000111xxxxx100000xxxxxxxxxx
swpalb. */
- return 1027;
+ return 1029;
}
else
{
@@ -1052,7 +1052,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000111xxxxx100000xxxxxxxxxx
swpalh. */
- return 1030;
+ return 1032;
}
}
else
@@ -1061,7 +1061,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000111xxxxx100000xxxxxxxxxx
swpal. */
- return 1033;
+ return 1035;
}
}
}
@@ -1083,7 +1083,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000001xxxxx010000xxxxxxxxxx
ldsmaxb. */
- return 1082;
+ return 1084;
}
else
{
@@ -1091,7 +1091,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000001xxxxx010000xxxxxxxxxx
ldsmaxh. */
- return 1083;
+ return 1085;
}
}
else
@@ -1100,7 +1100,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000001xxxxx010000xxxxxxxxxx
ldsmax. */
- return 1084;
+ return 1086;
}
}
else
@@ -1113,7 +1113,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000101xxxxx010000xxxxxxxxxx
ldsmaxab. */
- return 1085;
+ return 1087;
}
else
{
@@ -1121,7 +1121,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000101xxxxx010000xxxxxxxxxx
ldsmaxah. */
- return 1088;
+ return 1090;
}
}
else
@@ -1130,7 +1130,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000101xxxxx010000xxxxxxxxxx
ldsmaxa. */
- return 1091;
+ return 1093;
}
}
}
@@ -1146,7 +1146,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000011xxxxx010000xxxxxxxxxx
ldsmaxlb. */
- return 1086;
+ return 1088;
}
else
{
@@ -1154,7 +1154,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000011xxxxx010000xxxxxxxxxx
ldsmaxlh. */
- return 1089;
+ return 1091;
}
}
else
@@ -1163,7 +1163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000011xxxxx010000xxxxxxxxxx
ldsmaxl. */
- return 1092;
+ return 1094;
}
}
else
@@ -1176,7 +1176,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000111xxxxx010000xxxxxxxxxx
ldsmaxalb. */
- return 1087;
+ return 1089;
}
else
{
@@ -1184,7 +1184,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000111xxxxx010000xxxxxxxxxx
ldsmaxalh. */
- return 1090;
+ return 1092;
}
}
else
@@ -1193,7 +1193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000111xxxxx010000xxxxxxxxxx
ldsmaxal. */
- return 1093;
+ return 1095;
}
}
}
@@ -1246,7 +1246,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000001xxxxxx01000xxxxxxxxxx
ldeorb. */
- return 1058;
+ return 1060;
}
else
{
@@ -1254,7 +1254,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000001xxxxxx01000xxxxxxxxxx
ldeorh. */
- return 1059;
+ return 1061;
}
}
else
@@ -1263,7 +1263,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000001xxxxxx01000xxxxxxxxxx
ldeor. */
- return 1060;
+ return 1062;
}
}
else
@@ -1276,7 +1276,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000101xxxxxx01000xxxxxxxxxx
ldeorab. */
- return 1061;
+ return 1063;
}
else
{
@@ -1284,7 +1284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000101xxxxxx01000xxxxxxxxxx
ldeorah. */
- return 1064;
+ return 1066;
}
}
else
@@ -1293,7 +1293,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000101xxxxxx01000xxxxxxxxxx
ldeora. */
- return 1067;
+ return 1069;
}
}
}
@@ -1309,7 +1309,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000011xxxxxx01000xxxxxxxxxx
ldeorlb. */
- return 1062;
+ return 1064;
}
else
{
@@ -1317,7 +1317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000011xxxxxx01000xxxxxxxxxx
ldeorlh. */
- return 1065;
+ return 1067;
}
}
else
@@ -1326,7 +1326,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000011xxxxxx01000xxxxxxxxxx
ldeorl. */
- return 1068;
+ return 1070;
}
}
else
@@ -1339,7 +1339,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000111xxxxxx01000xxxxxxxxxx
ldeoralb. */
- return 1063;
+ return 1065;
}
else
{
@@ -1347,7 +1347,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000111xxxxxx01000xxxxxxxxxx
ldeoralh. */
- return 1066;
+ return 1068;
}
}
else
@@ -1356,7 +1356,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000111xxxxxx01000xxxxxxxxxx
ldeoral. */
- return 1069;
+ return 1071;
}
}
}
@@ -1375,7 +1375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000001xxxxxx11000xxxxxxxxxx
ldumaxb. */
- return 1106;
+ return 1108;
}
else
{
@@ -1383,7 +1383,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000001xxxxxx11000xxxxxxxxxx
ldumaxh. */
- return 1107;
+ return 1109;
}
}
else
@@ -1392,7 +1392,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000001xxxxxx11000xxxxxxxxxx
ldumax. */
- return 1108;
+ return 1110;
}
}
else
@@ -1405,7 +1405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000101xxxxxx11000xxxxxxxxxx
ldumaxab. */
- return 1109;
+ return 1111;
}
else
{
@@ -1413,7 +1413,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000101xxxxxx11000xxxxxxxxxx
ldumaxah. */
- return 1112;
+ return 1114;
}
}
else
@@ -1422,7 +1422,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000101xxxxxx11000xxxxxxxxxx
ldumaxa. */
- return 1115;
+ return 1117;
}
}
}
@@ -1438,7 +1438,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000011xxxxxx11000xxxxxxxxxx
ldumaxlb. */
- return 1110;
+ return 1112;
}
else
{
@@ -1446,7 +1446,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000011xxxxxx11000xxxxxxxxxx
ldumaxlh. */
- return 1113;
+ return 1115;
}
}
else
@@ -1455,7 +1455,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000011xxxxxx11000xxxxxxxxxx
ldumaxl. */
- return 1116;
+ return 1118;
}
}
else
@@ -1468,7 +1468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00111000111xxxxxx11000xxxxxxxxxx
ldumaxalb. */
- return 1111;
+ return 1113;
}
else
{
@@ -1476,7 +1476,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01111000111xxxxxx11000xxxxxxxxxx
ldumaxalh. */
- return 1114;
+ return 1116;
}
}
else
@@ -1485,7 +1485,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1x111000111xxxxxx11000xxxxxxxxxx
ldumaxal. */
- return 1117;
+ return 1119;
}
}
[...]
[diff truncated at 100000 bytes]