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[binutils-gdb] [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal feature macros
- From: Richard Earnshaw <rearnsha at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 9 Oct 2018 14:40:48 -0000
- Subject: [binutils-gdb] [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal feature macros
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=70d561813cd4da84109395c36662a187411a4d97
commit 70d561813cd4da84109395c36662a187411a4d97
Author: Sudakshina Das <sudi.das@arm.com>
Date: Wed Sep 26 10:38:59 2018 +0100
[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal feature macros
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This is the first of the patch series and adds -march=armv8.5-a and
other internal feature marcos needed for it.
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_archs): New entry for armv8.5-a.
* doc/c-aarch64.texi: Add documentation for the same.
*** include/ChnageLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
(AARCH64_ARCH_V8_5): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
(ARMV8_5, V8_5_INSN): New.
Diff:
---
gas/ChangeLog | 6 ++++++
gas/config/tc-aarch64.c | 1 +
gas/doc/c-aarch64.texi | 3 ++-
include/ChangeLog | 5 +++++
include/opcode/aarch64.h | 4 ++++
opcodes/ChangeLog | 5 +++++
opcodes/aarch64-tbl.h | 6 ++++++
7 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b531980..bed87c9 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,11 @@
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-aarch64.c (aarch64_archs): New entry for armv8.5-a.
+ * doc/c-aarch64.texi: Add documentation for the same.
+
2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
+
* testsuite/gas/i386/se1.s: Add enclv.
* testsuite/gas/i386/x86-64-se1.s: Likewise.
* testsuite/gas/i386/se1.d: Updated.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 085ffa2..9ae05e0 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8694,6 +8694,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
{"armv8.2-a", AARCH64_ARCH_V8_2},
{"armv8.3-a", AARCH64_ARCH_V8_3},
{"armv8.4-a", AARCH64_ARCH_V8_4},
+ {"armv8.5-a", AARCH64_ARCH_V8_5},
{NULL, AARCH64_ARCH_NONE}
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index b659b8b..bac0f77 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -91,7 +91,8 @@ This option specifies the target architecture. The assembler will
issue an error message if an attempt is made to assemble an
instruction which will not execute on the target architecture. The
following architecture names are recognized: @code{armv8-a},
-@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a} and @code{armv8.4-a}.
+@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
+and @code{armv8.5-a}.
If both @option{-mcpu} and @option{-march} are specified, the
assembler will use the setting for @option{-mcpu}. If neither are
diff --git a/include/ChangeLog b/include/ChangeLog
index ce95a61..2ccf741 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
+ (AARCH64_ARCH_V8_5): New.
+
2018-10-08 Alan Modra <amodra@gmail.com>
* bfdlink.h (struct bfd_link_info): Add load_phdrs field.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f66ee86..f8ae42f 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -62,6 +62,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
+#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -85,6 +86,9 @@ typedef uint32_t aarch64_insn;
AARCH64_FEATURE_V8_4 \
| AARCH64_FEATURE_DOTPROD \
| AARCH64_FEATURE_F16_FML)
+#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
+ AARCH64_FEATURE_V8_5)
+
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6407047..2b13be5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
+ (ARMV8_5, V8_5_INSN): New.
+
2018-10-08 Tamar Christina <tamar.christina@arm.com>
* aarch64-opc.c (verify_constraints): Use memset instead of {0}.
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 825324e..50a9a49 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2159,6 +2159,9 @@ static const aarch64_feature_set aarch64_feature_sha3 =
static const aarch64_feature_set aarch64_feature_fp_16_v8_2 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F16_FML
| AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
+static const aarch64_feature_set aarch64_feature_v8_5 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_5, 0);
+
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2186,6 +2189,7 @@ static const aarch64_feature_set aarch64_feature_fp_16_v8_2 =
#define CRYPTO_V8_2 &aarch64_feature_crypto_v8_2
#define FP_F16_V8_2 &aarch64_feature_fp_16_v8_2
#define DOTPROD &aarch64_feature_dotprod
+#define ARMV8_5 &aarch64_feature_v8_5
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2237,6 +2241,8 @@ static const aarch64_feature_set aarch64_feature_fp_16_v8_2 =
{ NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2, OPS, QUALS, FLAGS, 0, 0, NULL }
#define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define V8_5_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_5, OPS, QUALS, FLAGS, 0, 0, NULL }
struct aarch64_opcode aarch64_opcode_table[] =
{