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[binutils-gdb/binutils-2_31-branch] x86: Add Intel ENCLV to assembler and disassembler


https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=1ae25bf8c2b5164e8a7e581cc4a72d692f4fd85a

commit 1ae25bf8c2b5164e8a7e581cc4a72d692f4fd85a
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Fri Oct 5 11:56:42 2018 -0700

    x86: Add Intel ENCLV to assembler and disassembler
    
    gas/
    
    	* testsuite/gas/i386/se1.s: Add enclv.
    	* testsuite/gas/i386/x86-64-se1.s: Likewise.
    	* testsuite/gas/i386/se1.d: Updated.
    	* testsuite/gas/i386/x86-64-se1.d: Likewise.
    
    opcodes/
    
    	* i386-dis.c (rm_table): Add enclv.
    	* i386-opc.tbl: Add enclv.
    	* i386-tbl.h: Regenerated.
    
    (cherry picked from commit a4e78aa5fed5ba2cc343c76b78d062291a6fb659)

Diff:
---
 gas/ChangeLog                       |  7 +++++++
 gas/testsuite/gas/i386/se1.d        |  1 +
 gas/testsuite/gas/i386/se1.s        |  1 +
 gas/testsuite/gas/i386/x86-64-se1.d |  1 +
 gas/testsuite/gas/i386/x86-64-se1.s |  1 +
 opcodes/ChangeLog                   |  6 ++++++
 opcodes/i386-dis.c                  |  2 +-
 opcodes/i386-opc.tbl                |  1 +
 opcodes/i386-tbl.h                  | 14 ++++++++++++++
 9 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 682ccb0..f9d3bce 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* testsuite/gas/i386/se1.s: Add enclv.
+	* testsuite/gas/i386/x86-64-se1.s: Likewise.
+	* testsuite/gas/i386/se1.d: Updated.
+	* testsuite/gas/i386/x86-64-se1.d: Likewise.
+
 2018-09-18  Tamar Christina  <tamar.christina@arm.com>
 
 	* config/tc-aarch64.c (output_operand_error_report): Apply filtering to
diff --git a/gas/testsuite/gas/i386/se1.d b/gas/testsuite/gas/i386/se1.d
index ff2685c..d7800ab 100644
--- a/gas/testsuite/gas/i386/se1.d
+++ b/gas/testsuite/gas/i386/se1.d
@@ -10,4 +10,5 @@ Disassembly of section .text:
 0+ <_start>:
 [ 	]*[a-f0-9]+:	0f 01 cf             	encls  
 [ 	]*[a-f0-9]+:	0f 01 d7             	enclu  
+[ 	]*[a-f0-9]+:	0f 01 c0             	enclv  
 #pass
diff --git a/gas/testsuite/gas/i386/se1.s b/gas/testsuite/gas/i386/se1.s
index 1b57ac8..92d5795 100644
--- a/gas/testsuite/gas/i386/se1.s
+++ b/gas/testsuite/gas/i386/se1.s
@@ -5,3 +5,4 @@ _start:
 
 	encls
 	enclu
+	enclv
diff --git a/gas/testsuite/gas/i386/x86-64-se1.d b/gas/testsuite/gas/i386/x86-64-se1.d
index 29494f0..a515219 100644
--- a/gas/testsuite/gas/i386/x86-64-se1.d
+++ b/gas/testsuite/gas/i386/x86-64-se1.d
@@ -10,4 +10,5 @@ Disassembly of section .text:
 0+ <_start>:
 [ 	]*[a-f0-9]+:	0f 01 cf             	encls  
 [ 	]*[a-f0-9]+:	0f 01 d7             	enclu  
+[ 	]*[a-f0-9]+:	0f 01 c0             	enclv  
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-se1.s b/gas/testsuite/gas/i386/x86-64-se1.s
index 1b57ac8..92d5795 100644
--- a/gas/testsuite/gas/i386/x86-64-se1.s
+++ b/gas/testsuite/gas/i386/x86-64-se1.s
@@ -5,3 +5,4 @@ _start:
 
 	encls
 	enclu
+	enclv
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 25ddce1..caa8db2 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (rm_table): Add enclv.
+	* i386-opc.tbl: Add enclv.
+	* i386-tbl.h: Regenerated.
+
 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR gas/23418
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 42d219c..7843687 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -12321,7 +12321,7 @@ static const struct dis386 rm_table[][8] = {
   },
   {
     /* RM_0F01_REG_0 */
-    { Bad_Opcode },
+    { "enclv",		{ Skip_MODRM }, 0 },
     { "vmcall",		{ Skip_MODRM }, 0 },
     { "vmlaunch",	{ Skip_MODRM }, 0 },
     { "vmresume",	{ Skip_MODRM }, 0 },
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 84ade35..99f4d66 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -4100,6 +4100,7 @@ xsavec64, 1, 0xfc7, 0x4, 2, CpuXSAVEC|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No
 
 encls, 0, 0xf01cf, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 enclu, 0, 0xf01d7, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+enclv, 0, 0xf01c0, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
 // SGX instructions end.
 
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 5c37eea..42ac313 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -83658,6 +83658,20 @@ const insn_template i386_optab[] =
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0 } } } },
+  { "enclv", 0, 0xf01c0, None, 3,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0 } } } },
   { "vcvtpd2udqx", 2, 0x79, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0,


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