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[binutils-gdb] Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.
- From: Igor Tsimbalist <itsimbal at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 22 Nov 2017 14:41:47 -0000
- Subject: [binutils-gdb] Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=94b98370de3ee157e039f26865390b5994c47c3b
commit 94b98370de3ee157e039f26865390b5994c47c3b
Author: Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Date: Mon Nov 20 19:23:28 2017 +0300
Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.
* i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
* i386-tbl.h: Regenerate.
Diff:
---
opcodes/ChangeLog | 5 +++++
opcodes/i386-opc.tbl | 4 ++--
opcodes/i386-tbl.h | 4 ++--
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 595b0a4..9ca089c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+ * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
+ * i386-tbl.h: Regenerate.
+
+2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
* i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
* i386-tbl.h: Regenerate.
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index f91baff..ec478d7 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2614,8 +2614,8 @@ vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex=2|VexOpcode=2|V
vgf2p8affineqb, 4, 0x66ce, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
vgf2p8affineqb, 4, 0x66ce, None, 1, CpuAVX|CpuGFNI, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
-vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
+vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
+vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM, RegYMM }
// FSGSBASE, RDRND and F16C
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 10815b1..da12e28 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -62723,7 +62723,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0 } },
+ 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -62743,7 +62743,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0 } },
+ 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },