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[binutils-gdb] Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options (+aes and +sha2). The
- From: Nick Clifton <nickc at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 9 Nov 2017 11:23:49 -0000
- Subject: [binutils-gdb] Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options (+aes and +sha2). The
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b6b9ca0c3ec9589d0dd40b2b86ba748a361b48eb
commit b6b9ca0c3ec9589d0dd40b2b86ba748a361b48eb
Author: Tamar Christina <tamar.christina@arm.com>
Date: Thu Nov 9 11:21:31 2017 +0000
Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options (+aes and +sha2). The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions.
gas * config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a.
(aarch64_features): Added SM4 and SHA3.
include * opcode/aarch64.h:
(AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New.
(AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New.
opcodes * aarch64-tbl.h
(aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
(aarch64_feature_sm4, aarch64_feature_sha3): New.
(aarch64_feature_fp_16_v8_2): New.
(ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
(V8_4_INSN, CRYPTO_V8_2_INSN): New.
(SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
Diff:
---
gas/ChangeLog | 5 +++++
gas/config/tc-aarch64.c | 6 ++++++
include/ChangeLog | 6 ++++++
include/opcode/aarch64.h | 5 +++++
opcodes/ChangeLog | 10 ++++++++++
opcodes/aarch64-tbl.h | 27 +++++++++++++++++++++++++++
6 files changed, 59 insertions(+)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index ad1c10c..6589654 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a.
+ (aarch64_features): Add SM4 and SHA3.
+
2017-11-08 Tamar Christina <tamar.christina@arm.com>
* config/tc-aarch64.c
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ee3c586..054ee92 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8455,6 +8455,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
{"armv8.1-a", AARCH64_ARCH_V8_1},
{"armv8.2-a", AARCH64_ARCH_V8_2},
{"armv8.3-a", AARCH64_ARCH_V8_3},
+ {"armv8.4-a", AARCH64_ARCH_V8_4},
{NULL, AARCH64_ARCH_NONE}
};
@@ -8506,6 +8507,11 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_ARCH_NONE},
{"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES, 0),
AARCH64_ARCH_NONE},
+ {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0),
+ AARCH64_ARCH_NONE},
+ {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
+ | AARCH64_FEATURE_SHA3, 0),
+ AARCH64_ARCH_NONE},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};
diff --git a/include/ChangeLog b/include/ChangeLog
index c27ec9c..4e3002f 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,9 @@
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * opcode/aarch64.h:
+ (AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New.
+ (AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New.
+
2017-11-09 Nick Clifton <nickc@redhat.com>
* opcode/aarch64.h (aarch64_feature_set): Change type to unsigned
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index a597ebe..2038164 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -39,6 +39,9 @@ typedef uint32_t aarch64_insn;
/* The following bitmasks control CPU features. */
#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
+#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
+#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
+#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
@@ -77,6 +80,8 @@ typedef uint32_t aarch64_insn;
AARCH64_FEATURE_V8_3 \
| AARCH64_FEATURE_RCPC \
| AARCH64_FEATURE_COMPNUM)
+#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
+ AARCH64_FEATURE_V8_4)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ffa56bb..410df9c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h
+ (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
+ (aarch64_feature_sm4, aarch64_feature_sha3): New.
+ (aarch64_feature_fp_16_v8_2): New.
+ (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
+ (V8_4_INSN, CRYPTO_V8_2_INSN): New.
+ (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
+
2017-11-08 Tamar Christina <tamar.christina@arm.com>
* aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 9d4f3a4..a99f5f5 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2041,6 +2041,18 @@ static const aarch64_feature_set aarch64_feature_sha2 =
AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_SHA2, 0);
static const aarch64_feature_set aarch64_feature_aes =
AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_AES, 0);
+static const aarch64_feature_set aarch64_feature_v8_4 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_4, 0);
+static const aarch64_feature_set aarch64_feature_crypto_v8_2 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_CRYPTO, 0);
+static const aarch64_feature_set aarch64_feature_sm4 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SM4, 0);
+static const aarch64_feature_set aarch64_feature_sha3 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SHA2
+ | AARCH64_FEATURE_SHA3, 0);
+static const aarch64_feature_set aarch64_feature_fp_16_v8_2 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F16
+ | AARCH64_FEATURE_FP, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2062,6 +2074,11 @@ static const aarch64_feature_set aarch64_feature_aes =
#define RCPC &aarch64_feature_rcpc
#define SHA2 &aarch64_feature_sha2
#define AES &aarch64_feature_aes
+#define ARMV8_4 &aarch64_feature_v8_4
+#define SHA3 &aarch64_feature_sha3
+#define SM4 &aarch64_feature_sm4
+#define CRYPTO_V8_2 &aarch64_feature_crypto_v8_2
+#define FP_F16_V8_2 &aarch64_feature_fp_16_v8_2
#define DOTPROD &aarch64_feature_dotprod
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
@@ -2099,6 +2116,16 @@ static const aarch64_feature_set aarch64_feature_aes =
{ NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, NULL }
#define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, NULL }
+#define V8_4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_4, OPS, QUALS, FLAGS, 0, NULL }
+#define CRYPTO_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, CRYPTO_V8_2, OPS, QUALS, FLAGS, 0, NULL }
+#define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, NULL }
+#define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, NULL }
+#define FP16_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2, OPS, QUALS, FLAGS, 0, NULL }
#define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, NULL }