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[binutils-gdb] MIPS16/opcodes: Annotate instruction aliases
- From: Maciej W.Rozycki <macro at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 25 Apr 2017 10:59:24 -0000
- Subject: [binutils-gdb] MIPS16/opcodes: Annotate instruction aliases
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=6e3d1f0728d980a384c5aa63ce7f2ff3919c5024
commit 6e3d1f0728d980a384c5aa63ce7f2ff3919c5024
Author: Maciej W. Rozycki <macro@imgtec.com>
Date: Tue Apr 25 11:44:29 2017 +0100
MIPS16/opcodes: Annotate instruction aliases
Complement commit 986e18a5a9fd ("Add a second 'pinfo' member to
mips_opcode to extend number of available bits"),
<https://sourceware.org/ml/binutils/2005-01/msg00261.html>, and annotate
MIPS16 NOP, LA, DLA and the synthetic forms of LD and LW instructions as
aliases. These correspond to MOVE, and the PC-relative ADDIU, DADDIU,
LD and LW hardware instructions respectively.
binutils/
* testsuite/binutils-all/mips/mips16-alias.d: New test.
* testsuite/binutils-all/mips/mips16-noalias.d: New test.
* testsuite/binutils-all/mips/mips16-alias.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
opcodes/
* mips16-opc.c (AL): New macro.
(mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
of "ld" and "lw" as aliases.
Diff:
---
binutils/ChangeLog | 7 +++++++
binutils/testsuite/binutils-all/mips/mips.exp | 2 ++
binutils/testsuite/binutils-all/mips/mips16-alias.d | 15 +++++++++++++++
binutils/testsuite/binutils-all/mips/mips16-alias.s | 20 ++++++++++++++++++++
.../testsuite/binutils-all/mips/mips16-noalias.d | 16 ++++++++++++++++
opcodes/ChangeLog | 6 ++++++
opcodes/mips16-opc.c | 12 +++++++-----
7 files changed, 73 insertions(+), 5 deletions(-)
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index eb540fa..d5b515f 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,10 @@
+2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/binutils-all/mips/mips16-alias.d: New test.
+ * testsuite/binutils-all/mips/mips16-noalias.d: New test.
+ * testsuite/binutils-all/mips/mips16-alias.s: New test source.
+ * testsuite/binutils-all/mips/mips.exp: Run the new tests.
+
2017-04-23 Alan Modra <amodra@gmail.com>
PR 21418
diff --git a/binutils/testsuite/binutils-all/mips/mips.exp b/binutils/testsuite/binutils-all/mips/mips.exp
index 255d4f7..672515c 100644
--- a/binutils/testsuite/binutils-all/mips/mips.exp
+++ b/binutils/testsuite/binutils-all/mips/mips.exp
@@ -30,4 +30,6 @@ if [is_elf_format] {
run_dump_test "mips16-pcrel"
run_dump_test "mips16-extend-noinsn"
run_dump_test "mips16-extend-insn"
+ run_dump_test "mips16-alias"
+ run_dump_test "mips16-noalias"
}
diff --git a/binutils/testsuite/binutils-all/mips/mips16-alias.d b/binutils/testsuite/binutils-all/mips/mips16-alias.d
new file mode 100644
index 0000000..875615b
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips16-alias.d
@@ -0,0 +1,15 @@
+#PROG: objcopy
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS16 instruction alias disassembly
+#as: -32 -mips3
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> 0a08 la v0,00000020 <bar>
+[0-9a-f]+ <[^>]*> b207 lw v0,00000020 <bar>
+[0-9a-f]+ <[^>]*> fe47 dla v0,00000020 <bar>
+[0-9a-f]+ <[^>]*> fc43 ld v0,00000020 <bar>
+ \.\.\.
+ \.\.\.
diff --git a/binutils/testsuite/binutils-all/mips/mips16-alias.s b/binutils/testsuite/binutils-all/mips/mips16-alias.s
new file mode 100644
index 0000000..bda4f9e
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips16-alias.s
@@ -0,0 +1,20 @@
+ .text
+ .set mips16
+ .ent foo
+foo:
+ nop
+ la $2, bar
+ lw $2, bar
+ dla $2, bar
+ ld $2, bar
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
+
+ .type bar, @object
+bar:
+ .long 0
+ .size bar, . - bar
diff --git a/binutils/testsuite/binutils-all/mips/mips16-noalias.d b/binutils/testsuite/binutils-all/mips/mips16-noalias.d
new file mode 100644
index 0000000..76f61bd
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips16-noalias.d
@@ -0,0 +1,16 @@
+#PROG: objcopy
+#objdump: -M no-aliases -d --prefix-addresses --show-raw-insn
+#name: MIPS16 canonical alias disassembly
+#as: -32 -mips3
+#source: mips16-alias.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 6500 move zero,s0
+[0-9a-f]+ <[^>]*> 0a08 addiu v0,\$pc,32
+[0-9a-f]+ <[^>]*> b207 lw v0,28\(\$pc\)
+[0-9a-f]+ <[^>]*> fe47 daddiu v0,\$pc,28
+[0-9a-f]+ <[^>]*> fc43 ld v0,24\(\$pc\)
+ \.\.\.
+ \.\.\.
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index df765e4..9bc7a90 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (AL): New macro.
+ (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
+ of "ld" and "lw" as aliases.
+
2017-04-24 Tamar Christina <tamar.christina@arm.com>
* aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index 96746d8..7c8a0be 100644
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -145,6 +145,8 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
/* Use some short hand macros to keep down the length of the lines in
the opcodes table. */
+#define AL INSN2_ALIAS
+
#define UBD INSN_UNCOND_BRANCH_DELAY
#define WR_1 INSN_WRITE_1
@@ -188,8 +190,8 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
const struct mips_opcode mips16_opcodes[] =
{
/* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */
-{"nop", "", 0x6500, 0xffff, 0, SH|RD_16, I1, 0, 0 }, /* move $0,$Z */
-{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
+{"nop", "", 0x6500, 0xffff, 0, SH|RD_16|AL, I1, 0, 0 }, /* move $0,$Z */
+{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
{"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
@@ -234,7 +236,7 @@ const struct mips_opcode mips16_opcodes[] =
{"cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
{"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
-{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
+{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 },
{"daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
@@ -301,14 +303,14 @@ const struct mips_opcode mips16_opcodes[] =
{"lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
{"lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
{"ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
-{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
+{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 },
{"ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
{"ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 },
{"lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
{"lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
{"li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 },
{"lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
-{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
+{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
{"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
{"lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },