[binutils-gdb/binutils-2_28-branch] Sanitize RISC-V GAS help text, documentation

[Palmer Dabbelt <palmer at sourceware dot org>]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=49dfd6d9347ada18f5b21d7a9d24b43b77ed80b7

commit 49dfd6d9347ada18f5b21d7a9d24b43b77ed80b7
Author: Palmer Dabbelt <palmer@dabbelt.com>
Date:   Tue Mar 21 08:36:44 2017 -0700

    Sanitize RISC-V GAS help text, documentation
    
    It looks like I missed the GAS help text when going through all the
    documentation last time, so it printed some of the old-format (never
    upstream) arguments.  I fixed this, and when I went to check doc/ I
    noticed it was missing the '-fpic'/'-fno-pic' options.
    
    2017-03-21  Palmer Dabbbelt  <palmer@dabbelt.com>
    
            * config/tc-riscv.c (md_show_usage): Remove defuct -m32, -m64,
            -msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
            print an invalid default ISA string.
            * doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.

Diff:
---
 gas/ChangeLog         | 7 +++++++
 gas/config/tc-riscv.c | 9 ++-------
 gas/doc/c-riscv.texi  | 8 ++++++++
 3 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index ddcbdff..904e0b9 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2017-03-21  Palmer Dabbbelt  <palmer@dabbelt.com>
+
+	* config/tc-riscv.c (md_show_usage): Remove defuct -m32, -m64,
+	-msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
+	print an invalid default ISA string.
+	* doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
+
 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 
 	* config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 429ba2b..649c3e8 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2465,15 +2465,10 @@ md_show_usage (FILE *stream)
 {
   fprintf (stream, _("\
 RISC-V options:\n\
-  -m32           assemble RV32 code\n\
-  -m64           assemble RV64 code (default)\n\
   -fpic          generate position-independent code\n\
   -fno-pic       don't generate position-independent code (default)\n\
-  -msoft-float   don't use F registers for floating-point values\n\
-  -mhard-float   use F registers for floating-point values (default)\n\
-  -mno-rvc       disable the C extension for compressed instructions (default)\n\
-  -mrvc          enable the C extension for compressed instructions\n\
-  -march=ISA     set the RISC-V architecture, RV64IMAFD by default\n\
+  -march=ISA     set the RISC-V architecture\n\
+  -mabi=ABI      set the RISC-V ABI\n\
 "));
 }
 
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 0fa1b58..2efba4b 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -26,6 +26,14 @@ The following table lists all availiable RISC-V specific options
 @c man begin OPTIONS
 @table @gcctabopt
 
+@cindex @samp{-fpic} option, RISC-V
+@item -fpic
+Generate position-independent code
+
+@cindex @samp{-fno-pic} option, RISC-V
+@item -fno-pic
+Don't generate position-independent code (default)
+
 @cindex @samp{-march=ISA} option, RISC-V
 @item -march=ISA
 Select the base isa, as specified by ISA.  For example -march=rv32ima.