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[binutils-gdb] [AArch64] Add ARMv8.3 FCMLA and FCADD instructions
- From: Szabolcs Nagy <nsz at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 18 Nov 2016 10:03:49 -0000
- Subject: [binutils-gdb] [AArch64] Add ARMv8.3 FCMLA and FCADD instructions
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c2c4ff8d52a2cd3263a547b0384692498714aa1b
commit c2c4ff8d52a2cd3263a547b0384692498714aa1b
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Fri Nov 18 10:02:16 2016 +0000
[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.
These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
(enum aarch64_op): Add OP_FCMLA_ELEM.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
(aarch64_opcode_table): Add fcmla and fcadd.
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
(operand_general_constraint_met_p): Rotate and index range check.
(aarch64_print_operand): Handle rotate operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
Diff:
---
gas/ChangeLog | 9 +
gas/config/tc-aarch64.c | 3 +
gas/testsuite/gas/aarch64/advsimd-armv8_3.d | 33 +
gas/testsuite/gas/aarch64/advsimd-armv8_3.s | 36 +
gas/testsuite/gas/aarch64/illegal-fcmla.d | 2 +
gas/testsuite/gas/aarch64/illegal-fcmla.l | 17 +
gas/testsuite/gas/aarch64/illegal-fcmla.s | 25 +
include/ChangeLog | 6 +
include/opcode/aarch64.h | 5 +
opcodes/ChangeLog | 18 +
opcodes/aarch64-asm-2.c | 1016 +++----
opcodes/aarch64-asm.c | 50 +-
opcodes/aarch64-asm.h | 1 +
opcodes/aarch64-dis-2.c | 4279 ++++++++++++++-------------
opcodes/aarch64-dis.c | 42 +
opcodes/aarch64-dis.h | 1 +
opcodes/aarch64-opc-2.c | 110 +-
opcodes/aarch64-opc.c | 40 +-
opcodes/aarch64-opc.h | 3 +
opcodes/aarch64-tbl.h | 30 +
20 files changed, 3041 insertions(+), 2685 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 560a7bf..2ade09c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,14 @@
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+ * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
+ * testsuite/gas/aarch64/advsimd-armv8_3.d: New.
+ * testsuite/gas/aarch64/advsimd-armv8_3.s: New.
+ * testsuite/gas/aarch64/illegal-fcmla.s: New.
+ * testsuite/gas/aarch64/illegal-fcmla.l: New.
+ * testsuite/gas/aarch64/illegal-fcmla.d: New.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Add ldaprb, ldaprh, ldapr tests.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise.
* testsuite/gas/aarch64/illegal-ldapr.s: Likewise.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 9b19d76..7c518c7 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5561,6 +5561,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_UIMM7:
case AARCH64_OPND_SVE_UIMM8:
case AARCH64_OPND_SVE_UIMM8_53:
+ case AARCH64_OPND_IMM_ROT1:
+ case AARCH64_OPND_IMM_ROT2:
+ case AARCH64_OPND_IMM_ROT3:
po_imm_nc_or_fail ();
info->imm.value = val;
break;
diff --git a/gas/testsuite/gas/aarch64/advsimd-armv8_3.d b/gas/testsuite/gas/aarch64/advsimd-armv8_3.d
new file mode 100644
index 0000000..0e477e4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-armv8_3.d
@@ -0,0 +1,33 @@
+#as: -march=armv8.3-a
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+[^:]+: 6ec3c441 fcmla v1.2d, v2.2d, v3.2d, #0
+[^:]+: 6ec3cc41 fcmla v1.2d, v2.2d, v3.2d, #90
+[^:]+: 6ec3d441 fcmla v1.2d, v2.2d, v3.2d, #180
+[^:]+: 6ec3dc41 fcmla v1.2d, v2.2d, v3.2d, #270
+[^:]+: 2e83cc41 fcmla v1.2s, v2.2s, v3.2s, #90
+[^:]+: 6e83cc41 fcmla v1.4s, v2.4s, v3.4s, #90
+[^:]+: 2e43cc41 fcmla v1.4h, v2.4h, v3.4h, #90
+[^:]+: 6e43cc41 fcmla v1.8h, v2.8h, v3.8h, #90
+[^:]+: 6f831041 fcmla v1.4s, v2.4s, v3.s\[0\], #0
+[^:]+: 6f833041 fcmla v1.4s, v2.4s, v3.s\[0\], #90
+[^:]+: 6f835041 fcmla v1.4s, v2.4s, v3.s\[0\], #180
+[^:]+: 6f837041 fcmla v1.4s, v2.4s, v3.s\[0\], #270
+[^:]+: 6f833841 fcmla v1.4s, v2.4s, v3.s\[1\], #90
+[^:]+: 2f433041 fcmla v1.4h, v2.4h, v3.h\[0\], #90
+[^:]+: 2f633041 fcmla v1.4h, v2.4h, v3.h\[1\], #90
+[^:]+: 6f433041 fcmla v1.8h, v2.8h, v3.h\[0\], #90
+[^:]+: 6f633041 fcmla v1.8h, v2.8h, v3.h\[1\], #90
+[^:]+: 6f433841 fcmla v1.8h, v2.8h, v3.h\[2\], #90
+[^:]+: 6f633841 fcmla v1.8h, v2.8h, v3.h\[3\], #90
+[^:]+: 6ec3e441 fcadd v1.2d, v2.2d, v3.2d, #90
+[^:]+: 6ec3f441 fcadd v1.2d, v2.2d, v3.2d, #270
+[^:]+: 2e83e441 fcadd v1.2s, v2.2s, v3.2s, #90
+[^:]+: 6e83e441 fcadd v1.4s, v2.4s, v3.4s, #90
+[^:]+: 2e43e441 fcadd v1.4h, v2.4h, v3.4h, #90
+[^:]+: 6e43e441 fcadd v1.8h, v2.8h, v3.8h, #90
diff --git a/gas/testsuite/gas/aarch64/advsimd-armv8_3.s b/gas/testsuite/gas/aarch64/advsimd-armv8_3.s
new file mode 100644
index 0000000..bfb94e5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-armv8_3.s
@@ -0,0 +1,36 @@
+/* Test file for ARMv8.3 complex arithmetics instructions. */
+ .text
+
+ /* Three-same operands FCMLA. */
+ fcmla v1.2d, v2.2d, v3.2d, #0
+ fcmla v1.2d, v2.2d, v3.2d, #90
+ fcmla v1.2d, v2.2d, v3.2d, #180
+ fcmla v1.2d, v2.2d, v3.2d, #270
+
+ fcmla v1.2s, v2.2s, v3.2s, #90
+ fcmla v1.4s, v2.4s, v3.4s, #90
+ fcmla v1.4h, v2.4h, v3.4h, #90
+ fcmla v1.8h, v2.8h, v3.8h, #90
+
+ /* Indexed element FCMLA. */
+ fcmla v1.4s, v2.4s, v3.s[0], #0
+ fcmla v1.4s, v2.4s, v3.s[0], #90
+ fcmla v1.4s, v2.4s, v3.s[0], #180
+ fcmla v1.4s, v2.4s, v3.s[0], #270
+ fcmla v1.4s, v2.4s, v3.s[1], #90
+
+ fcmla v1.4h, v2.4h, v3.h[0], #90
+ fcmla v1.4h, v2.4h, v3.h[1], #90
+ fcmla v1.8h, v2.8h, v3.h[0], #90
+ fcmla v1.8h, v2.8h, v3.h[1], #90
+ fcmla v1.8h, v2.8h, v3.h[2], #90
+ fcmla v1.8h, v2.8h, v3.h[3], #90
+
+ /* Three-same operands FADD. */
+ fcadd v1.2d, v2.2d, v3.2d, #90
+ fcadd v1.2d, v2.2d, v3.2d, #270
+
+ fcadd v1.2s, v2.2s, v3.2s, #90
+ fcadd v1.4s, v2.4s, v3.4s, #90
+ fcadd v1.4h, v2.4h, v3.4h, #90
+ fcadd v1.8h, v2.8h, v3.8h, #90
diff --git a/gas/testsuite/gas/aarch64/illegal-fcmla.d b/gas/testsuite/gas/aarch64/illegal-fcmla.d
new file mode 100644
index 0000000..af94c51
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-fcmla.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.3-a -mno-verbose-error
+#error-output: illegal-fcmla.l
diff --git a/gas/testsuite/gas/aarch64/illegal-fcmla.l b/gas/testsuite/gas/aarch64/illegal-fcmla.l
new file mode 100644
index 0000000..1c0f1e4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-fcmla.l
@@ -0,0 +1,17 @@
+[^:]*: Assembler messages:
+[^:]+:10: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla v0\.4s,v1\.4s,v2\.s\[0\],#-90'
+[^:]+:11: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla v0\.4s,v1\.4s,v2\.s\[0\],#30'
+[^:]+:12: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla v0\.4s,v1\.4s,v2\.s\[0\],#360'
+[^:]+:13: Error: register element index out of range 0 to 1 at operand 3 -- `fcmla v0\.4h,v1\.4h,v2\.h\[2\],#90'
+[^:]+:14: Error: register element index out of range 0 to 3 at operand 3 -- `fcmla v0\.8h,v1\.8h,v2\.h\[4\],#90'
+[^:]+:15: Error: register element index out of range 0 to 1 at operand 3 -- `fcmla v0\.4s,v1\.4s,v2\.s\[2\],#90'
+[^:]+:16: Error: operand mismatch -- `fcmla v0\.2s,v1\.2s,v2\.s\[0\],#90'
+[^:]+:17: Error: operand mismatch -- `fcmla v0\.4s,v1\.4s,v2\.d\[0\],#90'
+[^:]+:18: Error: operand mismatch -- `fcmla v0\.2d,v1\.2d,v2\.d\[0\],#0'
+[^:]+:19: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla v0\.4s,v1\.4s,v2\.4s,#-90'
+[^:]+:20: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla v0\.4s,v1\.4s,v2\.4s,#30'
+[^:]+:21: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla v0\.4s,v1\.4s,v2\.4s,#360'
+[^:]+:22: Error: invalid element size 8 and vector size combination s at operand 1 -- `fcmla v0\.8s,v1\.8s,v2\.8s,#0'
+[^:]+:23: Error: operand mismatch -- `fcmla v0\.1d,v1\.1d,v2\.1d,#0'
+[^:]+:24: Error: rotate expected to be 90 or 270 at operand 4 -- `fcadd v0\.4h,v1\.4h,v2\.4h,#0'
+[^:]+:25: Error: rotate expected to be 90 or 270 at operand 4 -- `fcadd v0\.4h,v1\.4h,v2\.4h,#180'
diff --git a/gas/testsuite/gas/aarch64/illegal-fcmla.s b/gas/testsuite/gas/aarch64/illegal-fcmla.s
new file mode 100644
index 0000000..882c7ba
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-fcmla.s
@@ -0,0 +1,25 @@
+// Test illegal ARMv8.3 FCMLA and FCADD instructions with -march=armv8.3-a.
+.text
+
+ // Good.
+ fcmla v0.4s, v1.4s, v2.s[0], #90
+ fcmla v0.4s, v1.4s, v2.4s, #90
+ fcadd v0.4h, v1.4h, v2.4h, #90
+
+ // Bad.
+ fcmla v0.4s, v1.4s, v2.s[0], #-90
+ fcmla v0.4s, v1.4s, v2.s[0], #30
+ fcmla v0.4s, v1.4s, v2.s[0], #360
+ fcmla v0.4h, v1.4h, v2.h[2], #90
+ fcmla v0.8h, v1.8h, v2.h[4], #90
+ fcmla v0.4s, v1.4s, v2.s[2], #90
+ fcmla v0.2s, v1.2s, v2.s[0], #90
+ fcmla v0.4s, v1.4s, v2.d[0], #90
+ fcmla v0.2d, v1.2d, v2.d[0], #0
+ fcmla v0.4s, v1.4s, v2.4s, #-90
+ fcmla v0.4s, v1.4s, v2.4s, #30
+ fcmla v0.4s, v1.4s, v2.4s, #360
+ fcmla v0.8s, v1.8s, v2.8s, #0
+ fcmla v0.1d, v1.1d, v2.1d, #0
+ fcadd v0.4h, v1.4h, v2.4h, #0
+ fcadd v0.4h, v1.4h, v2.4h, #180
diff --git a/include/ChangeLog b/include/ChangeLog
index 9375bc8..8631956 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,11 @@
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+ * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
+ AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
+ (enum aarch64_op): Add OP_FCMLA_ELEM.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
(enum aarch64_insn_class): Add ldst_imm10.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index a35a813..69645d0 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -204,6 +204,9 @@ enum aarch64_opnd
AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
+ AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
+ AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
+ AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
AARCH64_OPND_COND, /* Standard condition as the last operand. */
AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
@@ -596,6 +599,8 @@ enum aarch64_op
OP_NOTS_P_P_P_Z,
OP_NOT_P_P_P_Z,
+ OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
+
OP_TOTAL_NUM, /* Pseudo. */
};
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e7911b1..b78e70d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,23 @@
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+ * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
+ (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
+ (aarch64_opcode_table): Add fcmla and fcadd.
+ (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
+ * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
+ * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
+ * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
+ * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
+ * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
+ * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
+ (operand_general_constraint_met_p): Rotate and index range check.
+ (aarch64_print_operand): Handle rotate operand.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Likewise.
+ * aarch64-opc-2.c: Likewise.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
* aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index d0358f9..121bde8 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -71,506 +71,506 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 24: /* subs */
value = 24; /* --> subs. */
break;
- case 150: /* mov */
- case 149: /* umov */
- value = 149; /* --> umov. */
- break;
- case 152: /* mov */
- case 151: /* ins */
- value = 151; /* --> ins. */
- break;
- case 154: /* mov */
- case 153: /* ins */
- value = 153; /* --> ins. */
- break;
- case 236: /* mvn */
- case 235: /* not */
- value = 235; /* --> not. */
- break;
- case 311: /* mov */
- case 310: /* orr */
- value = 310; /* --> orr. */
- break;
- case 380: /* sxtl */
- case 379: /* sshll */
- value = 379; /* --> sshll. */
- break;
- case 382: /* sxtl2 */
- case 381: /* sshll2 */
- value = 381; /* --> sshll2. */
- break;
- case 404: /* uxtl */
- case 403: /* ushll */
- value = 403; /* --> ushll. */
- break;
- case 406: /* uxtl2 */
- case 405: /* ushll2 */
- value = 405; /* --> ushll2. */
- break;
- case 527: /* mov */
- case 526: /* dup */
- value = 526; /* --> dup. */
- break;
- case 614: /* sxtw */
- case 613: /* sxth */
- case 612: /* sxtb */
- case 615: /* asr */
- case 611: /* sbfx */
- case 610: /* sbfiz */
- case 609: /* sbfm */
- value = 609; /* --> sbfm. */
- break;
- case 618: /* bfc */
- case 619: /* bfxil */
- case 617: /* bfi */
- case 616: /* bfm */
- value = 616; /* --> bfm. */
- break;
- case 624: /* uxth */
- case 623: /* uxtb */
- case 626: /* lsr */
- case 625: /* lsl */
- case 622: /* ubfx */
- case 621: /* ubfiz */
- case 620: /* ubfm */
- value = 620; /* --> ubfm. */
- break;
- case 656: /* cset */
- case 655: /* cinc */
- case 654: /* csinc */
- value = 654; /* --> csinc. */
- break;
- case 659: /* csetm */
- case 658: /* cinv */
- case 657: /* csinv */
- value = 657; /* --> csinv. */
- break;
- case 661: /* cneg */
- case 660: /* csneg */
- value = 660; /* --> csneg. */
- break;
- case 679: /* rev */
- case 680: /* rev64 */
- value = 679; /* --> rev. */
- break;
- case 705: /* lsl */
- case 704: /* lslv */
- value = 704; /* --> lslv. */
- break;
- case 707: /* lsr */
- case 706: /* lsrv */
- value = 706; /* --> lsrv. */
- break;
- case 709: /* asr */
- case 708: /* asrv */
- value = 708; /* --> asrv. */
- break;
- case 711: /* ror */
- case 710: /* rorv */
- value = 710; /* --> rorv. */
- break;
- case 722: /* mul */
- case 721: /* madd */
- value = 721; /* --> madd. */
- break;
- case 724: /* mneg */
- case 723: /* msub */
- value = 723; /* --> msub. */
- break;
- case 726: /* smull */
- case 725: /* smaddl */
- value = 725; /* --> smaddl. */
- break;
- case 728: /* smnegl */
- case 727: /* smsubl */
- value = 727; /* --> smsubl. */
- break;
- case 731: /* umull */
- case 730: /* umaddl */
- value = 730; /* --> umaddl. */
- break;
- case 733: /* umnegl */
- case 732: /* umsubl */
- value = 732; /* --> umsubl. */
- break;
- case 744: /* ror */
- case 743: /* extr */
- value = 743; /* --> extr. */
- break;
- case 957: /* bic */
- case 956: /* and */
- value = 956; /* --> and. */
- break;
- case 959: /* mov */
- case 958: /* orr */
- value = 958; /* --> orr. */
- break;
- case 962: /* tst */
- case 961: /* ands */
- value = 961; /* --> ands. */
- break;
- case 967: /* uxtw */
- case 966: /* mov */
- case 965: /* orr */
- value = 965; /* --> orr. */
- break;
- case 969: /* mvn */
- case 968: /* orn */
- value = 968; /* --> orn. */
- break;
- case 973: /* tst */
- case 972: /* ands */
- value = 972; /* --> ands. */
- break;
- case 1099: /* staddb */
- case 1003: /* ldaddb */
- value = 1003; /* --> ldaddb. */
- break;
- case 1100: /* staddh */
- case 1004: /* ldaddh */
- value = 1004; /* --> ldaddh. */
- break;
- case 1101: /* stadd */
- case 1005: /* ldadd */
- value = 1005; /* --> ldadd. */
+ case 151: /* mov */
+ case 150: /* umov */
+ value = 150; /* --> umov. */
+ break;
+ case 153: /* mov */
+ case 152: /* ins */
+ value = 152; /* --> ins. */
+ break;
+ case 155: /* mov */
+ case 154: /* ins */
+ value = 154; /* --> ins. */
+ break;
+ case 237: /* mvn */
+ case 236: /* not */
+ value = 236; /* --> not. */
+ break;
+ case 312: /* mov */
+ case 311: /* orr */
+ value = 311; /* --> orr. */
+ break;
+ case 383: /* sxtl */
+ case 382: /* sshll */
+ value = 382; /* --> sshll. */
+ break;
+ case 385: /* sxtl2 */
+ case 384: /* sshll2 */
+ value = 384; /* --> sshll2. */
+ break;
+ case 407: /* uxtl */
+ case 406: /* ushll */
+ value = 406; /* --> ushll. */
+ break;
+ case 409: /* uxtl2 */
+ case 408: /* ushll2 */
+ value = 408; /* --> ushll2. */
+ break;
+ case 530: /* mov */
+ case 529: /* dup */
+ value = 529; /* --> dup. */
+ break;
+ case 617: /* sxtw */
+ case 616: /* sxth */
+ case 615: /* sxtb */
+ case 618: /* asr */
+ case 614: /* sbfx */
+ case 613: /* sbfiz */
+ case 612: /* sbfm */
+ value = 612; /* --> sbfm. */
+ break;
+ case 621: /* bfc */
+ case 622: /* bfxil */
+ case 620: /* bfi */
+ case 619: /* bfm */
+ value = 619; /* --> bfm. */
+ break;
+ case 627: /* uxth */
+ case 626: /* uxtb */
+ case 629: /* lsr */
+ case 628: /* lsl */
+ case 625: /* ubfx */
+ case 624: /* ubfiz */
+ case 623: /* ubfm */
+ value = 623; /* --> ubfm. */
+ break;
+ case 659: /* cset */
+ case 658: /* cinc */
+ case 657: /* csinc */
+ value = 657; /* --> csinc. */
+ break;
+ case 662: /* csetm */
+ case 661: /* cinv */
+ case 660: /* csinv */
+ value = 660; /* --> csinv. */
+ break;
+ case 664: /* cneg */
+ case 663: /* csneg */
+ value = 663; /* --> csneg. */
+ break;
+ case 682: /* rev */
+ case 683: /* rev64 */
+ value = 682; /* --> rev. */
+ break;
+ case 708: /* lsl */
+ case 707: /* lslv */
+ value = 707; /* --> lslv. */
+ break;
+ case 710: /* lsr */
+ case 709: /* lsrv */
+ value = 709; /* --> lsrv. */
+ break;
+ case 712: /* asr */
+ case 711: /* asrv */
+ value = 711; /* --> asrv. */
+ break;
+ case 714: /* ror */
+ case 713: /* rorv */
+ value = 713; /* --> rorv. */
+ break;
+ case 725: /* mul */
+ case 724: /* madd */
+ value = 724; /* --> madd. */
+ break;
+ case 727: /* mneg */
+ case 726: /* msub */
+ value = 726; /* --> msub. */
+ break;
+ case 729: /* smull */
+ case 728: /* smaddl */
+ value = 728; /* --> smaddl. */
+ break;
+ case 731: /* smnegl */
+ case 730: /* smsubl */
+ value = 730; /* --> smsubl. */
+ break;
+ case 734: /* umull */
+ case 733: /* umaddl */
+ value = 733; /* --> umaddl. */
+ break;
+ case 736: /* umnegl */
+ case 735: /* umsubl */
+ value = 735; /* --> umsubl. */
+ break;
+ case 747: /* ror */
+ case 746: /* extr */
+ value = 746; /* --> extr. */
+ break;
+ case 960: /* bic */
+ case 959: /* and */
+ value = 959; /* --> and. */
+ break;
+ case 962: /* mov */
+ case 961: /* orr */
+ value = 961; /* --> orr. */
+ break;
+ case 965: /* tst */
+ case 964: /* ands */
+ value = 964; /* --> ands. */
+ break;
+ case 970: /* uxtw */
+ case 969: /* mov */
+ case 968: /* orr */
+ value = 968; /* --> orr. */
+ break;
+ case 972: /* mvn */
+ case 971: /* orn */
+ value = 971; /* --> orn. */
+ break;
+ case 976: /* tst */
+ case 975: /* ands */
+ value = 975; /* --> ands. */
+ break;
+ case 1102: /* staddb */
+ case 1006: /* ldaddb */
+ value = 1006; /* --> ldaddb. */
+ break;
+ case 1103: /* staddh */
+ case 1007: /* ldaddh */
+ value = 1007; /* --> ldaddh. */
+ break;
+ case 1104: /* stadd */
+ case 1008: /* ldadd */
+ value = 1008; /* --> ldadd. */
break;
- case 1102: /* staddlb */
- case 1007: /* ldaddlb */
- value = 1007; /* --> ldaddlb. */
+ case 1105: /* staddlb */
+ case 1010: /* ldaddlb */
+ value = 1010; /* --> ldaddlb. */
break;
- case 1103: /* staddlh */
- case 1010: /* ldaddlh */
- value = 1010; /* --> ldaddlh. */
+ case 1106: /* staddlh */
+ case 1013: /* ldaddlh */
+ value = 1013; /* --> ldaddlh. */
break;
- case 1104: /* staddl */
- case 1013: /* ldaddl */
- value = 1013; /* --> ldaddl. */
+ case 1107: /* staddl */
+ case 1016: /* ldaddl */
+ value = 1016; /* --> ldaddl. */
break;
- case 1105: /* stclrb */
- case 1015: /* ldclrb */
- value = 1015; /* --> ldclrb. */
+ case 1108: /* stclrb */
+ case 1018: /* ldclrb */
+ value = 1018; /* --> ldclrb. */
break;
- case 1106: /* stclrh */
- case 1016: /* ldclrh */
- value = 1016; /* --> ldclrh. */
+ case 1109: /* stclrh */
+ case 1019: /* ldclrh */
+ value = 1019; /* --> ldclrh. */
break;
- case 1107: /* stclr */
- case 1017: /* ldclr */
- value = 1017; /* --> ldclr. */
+ case 1110: /* stclr */
+ case 1020: /* ldclr */
+ value = 1020; /* --> ldclr. */
break;
- case 1108: /* stclrlb */
- case 1019: /* ldclrlb */
- value = 1019; /* --> ldclrlb. */
+ case 1111: /* stclrlb */
+ case 1022: /* ldclrlb */
+ value = 1022; /* --> ldclrlb. */
break;
- case 1109: /* stclrlh */
- case 1022: /* ldclrlh */
- value = 1022; /* --> ldclrlh. */
+ case 1112: /* stclrlh */
+ case 1025: /* ldclrlh */
+ value = 1025; /* --> ldclrlh. */
break;
- case 1110: /* stclrl */
- case 1025: /* ldclrl */
- value = 1025; /* --> ldclrl. */
+ case 1113: /* stclrl */
+ case 1028: /* ldclrl */
+ value = 1028; /* --> ldclrl. */
break;
- case 1111: /* steorb */
- case 1027: /* ldeorb */
- value = 1027; /* --> ldeorb. */
+ case 1114: /* steorb */
+ case 1030: /* ldeorb */
+ value = 1030; /* --> ldeorb. */
break;
- case 1112: /* steorh */
- case 1028: /* ldeorh */
- value = 1028; /* --> ldeorh. */
+ case 1115: /* steorh */
+ case 1031: /* ldeorh */
+ value = 1031; /* --> ldeorh. */
break;
- case 1113: /* steor */
- case 1029: /* ldeor */
- value = 1029; /* --> ldeor. */
+ case 1116: /* steor */
+ case 1032: /* ldeor */
+ value = 1032; /* --> ldeor. */
break;
- case 1114: /* steorlb */
- case 1031: /* ldeorlb */
- value = 1031; /* --> ldeorlb. */
+ case 1117: /* steorlb */
+ case 1034: /* ldeorlb */
+ value = 1034; /* --> ldeorlb. */
break;
- case 1115: /* steorlh */
- case 1034: /* ldeorlh */
- value = 1034; /* --> ldeorlh. */
+ case 1118: /* steorlh */
+ case 1037: /* ldeorlh */
+ value = 1037; /* --> ldeorlh. */
break;
- case 1116: /* steorl */
- case 1037: /* ldeorl */
- value = 1037; /* --> ldeorl. */
+ case 1119: /* steorl */
+ case 1040: /* ldeorl */
+ value = 1040; /* --> ldeorl. */
break;
- case 1117: /* stsetb */
- case 1039: /* ldsetb */
- value = 1039; /* --> ldsetb. */
+ case 1120: /* stsetb */
+ case 1042: /* ldsetb */
+ value = 1042; /* --> ldsetb. */
break;
- case 1118: /* stseth */
- case 1040: /* ldseth */
- value = 1040; /* --> ldseth. */
+ case 1121: /* stseth */
+ case 1043: /* ldseth */
+ value = 1043; /* --> ldseth. */
break;
- case 1119: /* stset */
- case 1041: /* ldset */
- value = 1041; /* --> ldset. */
+ case 1122: /* stset */
+ case 1044: /* ldset */
+ value = 1044; /* --> ldset. */
break;
- case 1120: /* stsetlb */
- case 1043: /* ldsetlb */
- value = 1043; /* --> ldsetlb. */
+ case 1123: /* stsetlb */
+ case 1046: /* ldsetlb */
+ value = 1046; /* --> ldsetlb. */
break;
- case 1121: /* stsetlh */
- case 1046: /* ldsetlh */
- value = 1046; /* --> ldsetlh. */
+ case 1124: /* stsetlh */
+ case 1049: /* ldsetlh */
+ value = 1049; /* --> ldsetlh. */
break;
- case 1122: /* stsetl */
- case 1049: /* ldsetl */
- value = 1049; /* --> ldsetl. */
+ case 1125: /* stsetl */
+ case 1052: /* ldsetl */
+ value = 1052; /* --> ldsetl. */
break;
- case 1123: /* stsmaxb */
- case 1051: /* ldsmaxb */
- value = 1051; /* --> ldsmaxb. */
+ case 1126: /* stsmaxb */
+ case 1054: /* ldsmaxb */
+ value = 1054; /* --> ldsmaxb. */
break;
- case 1124: /* stsmaxh */
- case 1052: /* ldsmaxh */
- value = 1052; /* --> ldsmaxh. */
+ case 1127: /* stsmaxh */
+ case 1055: /* ldsmaxh */
+ value = 1055; /* --> ldsmaxh. */
break;
- case 1125: /* stsmax */
- case 1053: /* ldsmax */
- value = 1053; /* --> ldsmax. */
- break;
- case 1126: /* stsmaxlb */
- case 1055: /* ldsmaxlb */
- value = 1055; /* --> ldsmaxlb. */
- break;
- case 1127: /* stsmaxlh */
- case 1058: /* ldsmaxlh */
- value = 1058; /* --> ldsmaxlh. */
- break;
- case 1128: /* stsmaxl */
- case 1061: /* ldsmaxl */
- value = 1061; /* --> ldsmaxl. */
- break;
- case 1129: /* stsminb */
- case 1063: /* ldsminb */
- value = 1063; /* --> ldsminb. */
- break;
- case 1130: /* stsminh */
- case 1064: /* ldsminh */
- value = 1064; /* --> ldsminh. */
- break;
- case 1131: /* stsmin */
- case 1065: /* ldsmin */
- value = 1065; /* --> ldsmin. */
- break;
- case 1132: /* stsminlb */
- case 1067: /* ldsminlb */
- value = 1067; /* --> ldsminlb. */
- break;
- case 1133: /* stsminlh */
- case 1070: /* ldsminlh */
- value = 1070; /* --> ldsminlh. */
- break;
- case 1134: /* stsminl */
- case 1073: /* ldsminl */
- value = 1073; /* --> ldsminl. */
- break;
- case 1135: /* stumaxb */
- case 1075: /* ldumaxb */
- value = 1075; /* --> ldumaxb. */
- break;
- case 1136: /* stumaxh */
- case 1076: /* ldumaxh */
- value = 1076; /* --> ldumaxh. */
- break;
- case 1137: /* stumax */
- case 1077: /* ldumax */
- value = 1077; /* --> ldumax. */
- break;
- case 1138: /* stumaxlb */
- case 1079: /* ldumaxlb */
- value = 1079; /* --> ldumaxlb. */
- break;
- case 1139: /* stumaxlh */
- case 1082: /* ldumaxlh */
- value = 1082; /* --> ldumaxlh. */
- break;
- case 1140: /* stumaxl */
- case 1085: /* ldumaxl */
- value = 1085; /* --> ldumaxl. */
- break;
- case 1141: /* stuminb */
- case 1087: /* lduminb */
- value = 1087; /* --> lduminb. */
- break;
- case 1142: /* stuminh */
- case 1088: /* lduminh */
- value = 1088; /* --> lduminh. */
- break;
- case 1143: /* stumin */
- case 1089: /* ldumin */
- value = 1089; /* --> ldumin. */
- break;
- case 1144: /* stuminlb */
- case 1091: /* lduminlb */
- value = 1091; /* --> lduminlb. */
- break;
- case 1145: /* stuminlh */
- case 1094: /* lduminlh */
- value = 1094; /* --> lduminlh. */
- break;
- case 1146: /* stuminl */
- case 1097: /* lduminl */
- value = 1097; /* --> lduminl. */
- break;
- case 1148: /* mov */
- case 1147: /* movn */
- value = 1147; /* --> movn. */
- break;
- case 1150: /* mov */
- case 1149: /* movz */
- value = 1149; /* --> movz. */
- break;
- case 1188: /* autibsp */
- case 1187: /* autibz */
- case 1186: /* autiasp */
- case 1185: /* autiaz */
- case 1184: /* pacibsp */
- case 1183: /* pacibz */
- case 1182: /* paciasp */
- case 1181: /* paciaz */
- case 1168: /* psb */
- case 1167: /* esb */
- case 1166: /* autib1716 */
- case 1165: /* autia1716 */
- case 1164: /* pacib1716 */
- case 1163: /* pacia1716 */
- case 1162: /* xpaclri */
- case 1161: /* sevl */
- case 1160: /* sev */
- case 1159: /* wfi */
- case 1158: /* wfe */
- case 1157: /* yield */
- case 1156: /* nop */
- case 1155: /* hint */
- value = 1155; /* --> hint. */
- break;
- case 1177: /* tlbi */
- case 1176: /* ic */
- case 1175: /* dc */
- case 1174: /* at */
- case 1173: /* sys */
- value = 1173; /* --> sys. */
- break;
- case 1931: /* bic */
- case 1236: /* and */
- value = 1236; /* --> and. */
+ case 1128: /* stsmax */
+ case 1056: /* ldsmax */
+ value = 1056; /* --> ldsmax. */
+ break;
+ case 1129: /* stsmaxlb */
+ case 1058: /* ldsmaxlb */
+ value = 1058; /* --> ldsmaxlb. */
+ break;
+ case 1130: /* stsmaxlh */
+ case 1061: /* ldsmaxlh */
+ value = 1061; /* --> ldsmaxlh. */
+ break;
+ case 1131: /* stsmaxl */
+ case 1064: /* ldsmaxl */
+ value = 1064; /* --> ldsmaxl. */
+ break;
+ case 1132: /* stsminb */
+ case 1066: /* ldsminb */
+ value = 1066; /* --> ldsminb. */
+ break;
+ case 1133: /* stsminh */
+ case 1067: /* ldsminh */
+ value = 1067; /* --> ldsminh. */
+ break;
+ case 1134: /* stsmin */
+ case 1068: /* ldsmin */
+ value = 1068; /* --> ldsmin. */
+ break;
+ case 1135: /* stsminlb */
+ case 1070: /* ldsminlb */
+ value = 1070; /* --> ldsminlb. */
+ break;
+ case 1136: /* stsminlh */
+ case 1073: /* ldsminlh */
+ value = 1073; /* --> ldsminlh. */
+ break;
+ case 1137: /* stsminl */
+ case 1076: /* ldsminl */
+ value = 1076; /* --> ldsminl. */
+ break;
+ case 1138: /* stumaxb */
+ case 1078: /* ldumaxb */
+ value = 1078; /* --> ldumaxb. */
+ break;
+ case 1139: /* stumaxh */
+ case 1079: /* ldumaxh */
+ value = 1079; /* --> ldumaxh. */
+ break;
+ case 1140: /* stumax */
+ case 1080: /* ldumax */
+ value = 1080; /* --> ldumax. */
+ break;
+ case 1141: /* stumaxlb */
+ case 1082: /* ldumaxlb */
+ value = 1082; /* --> ldumaxlb. */
+ break;
+ case 1142: /* stumaxlh */
+ case 1085: /* ldumaxlh */
+ value = 1085; /* --> ldumaxlh. */
+ break;
+ case 1143: /* stumaxl */
+ case 1088: /* ldumaxl */
+ value = 1088; /* --> ldumaxl. */
+ break;
+ case 1144: /* stuminb */
+ case 1090: /* lduminb */
+ value = 1090; /* --> lduminb. */
+ break;
+ case 1145: /* stuminh */
+ case 1091: /* lduminh */
+ value = 1091; /* --> lduminh. */
+ break;
+ case 1146: /* stumin */
+ case 1092: /* ldumin */
+ value = 1092; /* --> ldumin. */
+ break;
+ case 1147: /* stuminlb */
+ case 1094: /* lduminlb */
+ value = 1094; /* --> lduminlb. */
+ break;
+ case 1148: /* stuminlh */
+ case 1097: /* lduminlh */
+ value = 1097; /* --> lduminlh. */
+ break;
+ case 1149: /* stuminl */
+ case 1100: /* lduminl */
+ value = 1100; /* --> lduminl. */
+ break;
+ case 1151: /* mov */
+ case 1150: /* movn */
+ value = 1150; /* --> movn. */
+ break;
+ case 1153: /* mov */
+ case 1152: /* movz */
+ value = 1152; /* --> movz. */
+ break;
+ case 1191: /* autibsp */
+ case 1190: /* autibz */
+ case 1189: /* autiasp */
+ case 1188: /* autiaz */
+ case 1187: /* pacibsp */
+ case 1186: /* pacibz */
+ case 1185: /* paciasp */
+ case 1184: /* paciaz */
+ case 1171: /* psb */
+ case 1170: /* esb */
+ case 1169: /* autib1716 */
+ case 1168: /* autia1716 */
+ case 1167: /* pacib1716 */
+ case 1166: /* pacia1716 */
+ case 1165: /* xpaclri */
+ case 1164: /* sevl */
+ case 1163: /* sev */
+ case 1162: /* wfi */
+ case 1161: /* wfe */
+ case 1160: /* yield */
+ case 1159: /* nop */
+ case 1158: /* hint */
+ value = 1158; /* --> hint. */
+ break;
+ case 1180: /* tlbi */
+ case 1179: /* ic */
+ case 1178: /* dc */
+ case 1177: /* at */
+ case 1176: /* sys */
+ value = 1176; /* --> sys. */
+ break;
+ case 1934: /* bic */
+ case 1239: /* and */
+ value = 1239; /* --> and. */
+ break;
+ case 1222: /* mov */
+ case 1241: /* and */
+ value = 1241; /* --> and. */
+ break;
+ case 1226: /* movs */
+ case 1242: /* ands */
+ value = 1242; /* --> ands. */
+ break;
+ case 1935: /* cmple */
+ case 1277: /* cmpge */
+ value = 1277; /* --> cmpge. */
+ break;
+ case 1938: /* cmplt */
+ case 1280: /* cmpgt */
+ value = 1280; /* --> cmpgt. */
+ break;
+ case 1936: /* cmplo */
+ case 1282: /* cmphi */
+ value = 1282; /* --> cmphi. */
+ break;
+ case 1937: /* cmpls */
+ case 1285: /* cmphs */
+ value = 1285; /* --> cmphs. */
break;
case 1219: /* mov */
- case 1238: /* and */
- value = 1238; /* --> and. */
+ case 1307: /* cpy */
+ value = 1307; /* --> cpy. */
break;
- case 1223: /* movs */
- case 1239: /* ands */
- value = 1239; /* --> ands. */
- break;
- case 1932: /* cmple */
- case 1274: /* cmpge */
- value = 1274; /* --> cmpge. */
- break;
- case 1935: /* cmplt */
- case 1277: /* cmpgt */
- value = 1277; /* --> cmpgt. */
+ case 1221: /* mov */
+ case 1308: /* cpy */
+ value = 1308; /* --> cpy. */
break;
- case 1933: /* cmplo */
- case 1279: /* cmphi */
- value = 1279; /* --> cmphi. */
+ case 1945: /* fmov */
+ case 1224: /* mov */
+ case 1309: /* cpy */
+ value = 1309; /* --> cpy. */
break;
- case 1934: /* cmpls */
- case 1282: /* cmphs */
- value = 1282; /* --> cmphs. */
+ case 1214: /* mov */
+ case 1321: /* dup */
+ value = 1321; /* --> dup. */
break;
case 1216: /* mov */
- case 1304: /* cpy */
- value = 1304; /* --> cpy. */
- break;
- case 1218: /* mov */
- case 1305: /* cpy */
- value = 1305; /* --> cpy. */
- break;
- case 1942: /* fmov */
- case 1221: /* mov */
- case 1306: /* cpy */
- value = 1306; /* --> cpy. */
- break;
- case 1211: /* mov */
- case 1318: /* dup */
- value = 1318; /* --> dup. */
- break;
case 1213: /* mov */
- case 1210: /* mov */
- case 1319: /* dup */
- value = 1319; /* --> dup. */
- break;
- case 1941: /* fmov */
- case 1215: /* mov */
- case 1320: /* dup */
- value = 1320; /* --> dup. */
- break;
- case 1214: /* mov */
- case 1321: /* dupm */
- value = 1321; /* --> dupm. */
+ case 1322: /* dup */
+ value = 1322; /* --> dup. */
break;
- case 1936: /* eon */
- case 1323: /* eor */
- value = 1323; /* --> eor. */
+ case 1944: /* fmov */
+ case 1218: /* mov */
+ case 1323: /* dup */
+ value = 1323; /* --> dup. */
break;
- case 1224: /* not */
- case 1325: /* eor */
- value = 1325; /* --> eor. */
+ case 1217: /* mov */
+ case 1324: /* dupm */
+ value = 1324; /* --> dupm. */
break;
- case 1225: /* nots */
- case 1326: /* eors */
- value = 1326; /* --> eors. */
+ case 1939: /* eon */
+ case 1326: /* eor */
+ value = 1326; /* --> eor. */
break;
- case 1937: /* facle */
- case 1331: /* facge */
- value = 1331; /* --> facge. */
+ case 1227: /* not */
+ case 1328: /* eor */
+ value = 1328; /* --> eor. */
break;
- case 1938: /* faclt */
- case 1332: /* facgt */
- value = 1332; /* --> facgt. */
+ case 1228: /* nots */
+ case 1329: /* eors */
+ value = 1329; /* --> eors. */
break;
- case 1939: /* fcmle */
- case 1341: /* fcmge */
- value = 1341; /* --> fcmge. */
+ case 1940: /* facle */
+ case 1334: /* facge */
+ value = 1334; /* --> facge. */
break;
- case 1940: /* fcmlt */
- case 1343: /* fcmgt */
- value = 1343; /* --> fcmgt. */
+ case 1941: /* faclt */
+ case 1335: /* facgt */
+ value = 1335; /* --> facgt. */
break;
- case 1208: /* fmov */
- case 1349: /* fcpy */
- value = 1349; /* --> fcpy. */
+ case 1942: /* fcmle */
+ case 1344: /* fcmge */
+ value = 1344; /* --> fcmge. */
break;
- case 1207: /* fmov */
- case 1366: /* fdup */
- value = 1366; /* --> fdup. */
+ case 1943: /* fcmlt */
+ case 1346: /* fcmgt */
+ value = 1346; /* --> fcmgt. */
break;
- case 1209: /* mov */
- case 1664: /* orr */
- value = 1664; /* --> orr. */
+ case 1211: /* fmov */
+ case 1352: /* fcpy */
+ value = 1352; /* --> fcpy. */
break;
- case 1943: /* orn */
- case 1665: /* orr */
- value = 1665; /* --> orr. */
+ case 1210: /* fmov */
+ case 1369: /* fdup */
+ value = 1369; /* --> fdup. */
break;
case 1212: /* mov */
case 1667: /* orr */
value = 1667; /* --> orr. */
break;
- case 1222: /* movs */
- case 1668: /* orrs */
- value = 1668; /* --> orrs. */
+ case 1946: /* orn */
+ case 1668: /* orr */
+ value = 1668; /* --> orr. */
break;
- case 1217: /* mov */
- case 1724: /* sel */
- value = 1724; /* --> sel. */
+ case 1215: /* mov */
+ case 1670: /* orr */
+ value = 1670; /* --> orr. */
+ break;
+ case 1225: /* movs */
+ case 1671: /* orrs */
+ value = 1671; /* --> orrs. */
break;
case 1220: /* mov */
- case 1725: /* sel */
- value = 1725; /* --> sel. */
+ case 1727: /* sel */
+ value = 1727; /* --> sel. */
+ break;
+ case 1223: /* mov */
+ case 1728: /* sel */
+ value = 1728; /* --> sel. */
break;
default: return NULL;
}
@@ -613,9 +613,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 28:
case 36:
case 37:
- case 141:
- case 142:
- case 143:
case 144:
case 145:
case 146:
@@ -623,9 +620,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 148:
case 149:
case 150:
- case 163:
- case 164:
- case 165:
+ case 151:
+ case 152:
+ case 153:
case 166:
case 167:
case 168:
@@ -633,7 +630,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 170:
case 171:
case 172:
+ case 173:
+ case 174:
case 175:
+ case 178:
return aarch64_ins_regno (self, info, code, inst);
case 13:
return aarch64_ins_reg_extended (self, info, code, inst);
@@ -667,20 +667,20 @@ aarch64_insert_operand (const aarch64_operand *self,
case 58:
case 59:
case 60:
- case 69:
- case 70:
- case 71:
case 72:
- case 138:
- case 140:
- case 155:
- case 156:
- case 157:
+ case 73:
+ case 74:
+ case 75:
+ case 141:
+ case 143:
case 158:
case 159:
case 160:
case 161:
case 162:
+ case 163:
+ case 164:
+ case 165:
return aarch64_ins_imm (self, info, code, inst);
case 39:
case 40:
@@ -690,10 +690,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 43:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
case 47:
- case 131:
+ case 134:
return aarch64_ins_fpimm (self, info, code, inst);
case 61:
- case 136:
+ case 139:
return aarch64_ins_limm (self, info, code, inst);
case 62:
return aarch64_ins_aimm (self, info, code, inst);
@@ -703,55 +703,56 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst);
case 66:
case 67:
+ case 68:
+ return aarch64_ins_imm_rotate (self, info, code, inst);
+ case 69:
+ case 70:
return aarch64_ins_cond (self, info, code, inst);
- case 73:
- case 80:
- return aarch64_ins_addr_simple (self, info, code, inst);
- case 74:
- return aarch64_ins_addr_regoff (self, info, code, inst);
- case 75:
case 76:
+ case 83:
+ return aarch64_ins_addr_simple (self, info, code, inst);
case 77:
- return aarch64_ins_addr_simm (self, info, code, inst);
+ return aarch64_ins_addr_regoff (self, info, code, inst);
case 78:
- return aarch64_ins_addr_simm10 (self, info, code, inst);
case 79:
- return aarch64_ins_addr_uimm12 (self, info, code, inst);
+ case 80:
+ return aarch64_ins_addr_simm (self, info, code, inst);
case 81:
- return aarch64_ins_simd_addr_post (self, info, code, inst);
+ return aarch64_ins_addr_simm10 (self, info, code, inst);
case 82:
- return aarch64_ins_sysreg (self, info, code, inst);
- case 83:
- return aarch64_ins_pstatefield (self, info, code, inst);
+ return aarch64_ins_addr_uimm12 (self, info, code, inst);
case 84:
+ return aarch64_ins_simd_addr_post (self, info, code, inst);
case 85:
+ return aarch64_ins_sysreg (self, info, code, inst);
case 86:
+ return aarch64_ins_pstatefield (self, info, code, inst);
case 87:
- return aarch64_ins_sysins_op (self, info, code, inst);
case 88:
case 89:
- return aarch64_ins_barrier (self, info, code, inst);
case 90:
- return aarch64_ins_prfop (self, info, code, inst);
+ return aarch64_ins_sysins_op (self, info, code, inst);
case 91:
- return aarch64_ins_hint (self, info, code, inst);
case 92:
+ return aarch64_ins_barrier (self, info, code, inst);
case 93:
+ return aarch64_ins_prfop (self, info, code, inst);
case 94:
+ return aarch64_ins_hint (self, info, code, inst);
case 95:
- return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
case 96:
- return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
case 97:
- return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
case 98:
+ return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
case 99:
+ return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
case 100:
+ return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
case 101:
- return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
case 102:
case 103:
case 104:
+ return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
case 105:
case 106:
case 107:
@@ -761,53 +762,56 @@ aarch64_insert_operand (const aarch64_operand *self,
case 111:
case 112:
case 113:
- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
case 114:
case 115:
case 116:
+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
case 117:
case 118:
case 119:
case 120:
case 121:
- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
case 122:
case 123:
case 124:
+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
case 125:
- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
case 126:
- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
case 127:
- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
case 128:
- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
case 129:
- return aarch64_ins_sve_aimm (self, info, code, inst);
+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
case 130:
- return aarch64_ins_sve_asimm (self, info, code, inst);
+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
+ case 131:
+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
case 132:
- return aarch64_ins_sve_float_half_one (self, info, code, inst);
+ return aarch64_ins_sve_aimm (self, info, code, inst);
case 133:
+ return aarch64_ins_sve_asimm (self, info, code, inst);
+ case 135:
+ return aarch64_ins_sve_float_half_one (self, info, code, inst);
+ case 136:
return aarch64_ins_sve_float_half_two (self, info, code, inst);
- case 134:
+ case 137:
return aarch64_ins_sve_float_zero_one (self, info, code, inst);
- case 135:
+ case 138:
return aarch64_ins_inv_limm (self, info, code, inst);
- case 137:
+ case 140:
return aarch64_ins_sve_limm_mov (self, info, code, inst);
- case 139:
+ case 142:
return aarch64_ins_sve_scale (self, info, code, inst);
- case 151:
- case 152:
- return aarch64_ins_sve_shlimm (self, info, code, inst);
- case 153:
case 154:
+ case 155:
+ return aarch64_ins_sve_shlimm (self, info, code, inst);
+ case 156:
+ case 157:
return aarch64_ins_sve_shrimm (self, info, code, inst);
- case 173:
- return aarch64_ins_sve_index (self, info, code, inst);
- case 174:
case 176:
+ return aarch64_ins_sve_index (self, info, code, inst);
+ case 177:
+ case 179:
return aarch64_ins_sve_reglist (self, info, code, inst);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 64051a9..cfe6630 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -125,19 +125,28 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
{
/* index for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
+ unsigned index = info->reglane.index;
+
+ if (inst->opcode->op == OP_FCMLA_ELEM)
+ /* Complex operand takes two elements. */
+ index *= 2;
+
switch (info->qualifier)
{
case AARCH64_OPND_QLF_S_H:
/* H:L:M */
- insert_fields (code, info->reglane.index, 0, 3, FLD_M, FLD_L, FLD_H);
+ assert (index < 8);
+ insert_fields (code, index, 0, 3, FLD_M, FLD_L, FLD_H);
break;
case AARCH64_OPND_QLF_S_S:
/* H:L */
- insert_fields (code, info->reglane.index, 0, 2, FLD_L, FLD_H);
+ assert (index < 4);
+ insert_fields (code, index, 0, 2, FLD_L, FLD_H);
break;
case AARCH64_OPND_QLF_S_D:
/* H */
- insert_field (FLD_H, code, info->reglane.index, 0);
+ assert (index < 2);
+ insert_field (FLD_H, code, index, 0);
break;
default:
assert (0);
@@ -427,6 +436,41 @@ aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info,
return NULL;
}
+/* Insert field rot for the rotate immediate in
+ FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>. */
+const char *
+aarch64_ins_imm_rotate (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code, const aarch64_inst *inst)
+{
+ uint64_t rot = info->imm.value / 90;
+
+ switch (info->type)
+ {
+ case AARCH64_OPND_IMM_ROT1:
+ case AARCH64_OPND_IMM_ROT2:
+ /* value rot
+ 0 0
+ 90 1
+ 180 2
+ 270 3 */
+ assert (rot < 4U);
+ break;
+ case AARCH64_OPND_IMM_ROT3:
+ /* value rot
+ 90 0
+ 270 1 */
+ rot = (rot - 1) / 2;
+ assert (rot < 2U);
+ break;
+ default:
+ assert (0);
+ }
+ insert_field (self->fields[0], code, rot, inst->opcode->mask);
+
+ return NULL;
+}
+
/* Insert #<fbits> for the immediate operand in fp fix-point instructions,
e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
const char *
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index b49d3d5..7fce657 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -92,6 +92,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
+AARCH64_DECL_OPD_INSERTER (ins_imm_rotate);
#undef AARCH64_DECL_OPD_INSERTER
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index a6391b0..19b3dcf 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -40,7 +40,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx0000xxx0
adr. */
- return 1152;
+ return 1155;
}
else
{
@@ -48,7 +48,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx0000xxx1
adrp. */
- return 1153;
+ return 1156;
}
}
else
@@ -115,7 +115,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx000x0010000
stxrb. */
- return 907;
+ return 910;
}
else
{
@@ -123,7 +123,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx000x0010010
stxrh. */
- return 913;
+ return 916;
}
}
else
@@ -132,7 +132,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx000x00100x1
stxr. */
- return 919;
+ return 922;
}
}
else
@@ -143,7 +143,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx100x00100x0
casp. */
- return 987;
+ return 990;
}
else
{
@@ -151,7 +151,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx100x00100x1
stxp. */
- return 921;
+ return 924;
}
}
}
@@ -167,7 +167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx000x0010000
stlxrb. */
- return 908;
+ return 911;
}
else
{
@@ -175,7 +175,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx000x0010010
stlxrh. */
- return 914;
+ return 917;
}
}
else
@@ -184,7 +184,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx000x00100x1
stlxr. */
- return 920;
+ return 923;
}
}
else
@@ -195,7 +195,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx100x00100x0
caspl. */
- return 989;
+ return 992;
}
else
{
@@ -203,7 +203,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx100x00100x1
stlxp. */
- return 922;
+ return 925;
}
}
}
@@ -214,7 +214,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxx00x00101xx
stnp. */
- return 938;
+ return 941;
}
}
else
@@ -231,7 +231,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx001x00100x0
stllrb. */
- return 936;
+ return 939;
}
else
{
@@ -239,7 +239,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx001x00100x1
stllr. */
- return 935;
+ return 938;
}
}
else
@@ -252,7 +252,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx101x0010000
casb. */
- return 975;
+ return 978;
}
else
{
@@ -260,7 +260,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx101x0010010
cash. */
- return 976;
+ return 979;
}
}
else
@@ -269,7 +269,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx101x00100x1
cas. */
- return 977;
+ return 980;
}
}
}
@@ -285,7 +285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx001x0010000
stlrb. */
- return 911;
+ return 914;
}
else
{
@@ -293,7 +293,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx001x0010010
stlrh. */
- return 917;
+ return 920;
}
}
else
@@ -302,7 +302,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx001x00100x1
stlr. */
- return 927;
+ return 930;
}
}
else
@@ -315,7 +315,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx101x0010000
caslb. */
- return 979;
+ return 982;
}
else
{
@@ -323,7 +323,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx101x0010010
caslh. */
- return 982;
+ return 985;
}
}
else
@@ -332,7 +332,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx101x00100x1
casl. */
- return 985;
+ return 988;
}
}
}
@@ -343,7 +343,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxx01x00101xx
stp. */
- return 947;
+ return 950;
}
}
}
@@ -365,7 +365,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx010x0010000
ldxrb. */
- return 909;
+ return 912;
}
else
{
@@ -373,7 +373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx010x0010010
ldxrh. */
- return 915;
+ return 918;
}
}
else
@@ -382,7 +382,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx010x00100x1
ldxr. */
- return 923;
+ return 926;
}
}
else
@@ -393,7 +393,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx110x00100x0
caspa. */
- return 988;
+ return 991;
}
else
{
@@ -401,7 +401,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx110x00100x1
ldxp. */
- return 925;
+ return 928;
}
}
}
@@ -417,7 +417,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx010x0010000
ldaxrb. */
- return 910;
+ return 913;
}
else
{
@@ -425,7 +425,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx010x0010010
ldaxrh. */
- return 916;
+ return 919;
}
}
else
@@ -434,7 +434,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx010x00100x1
ldaxr. */
- return 924;
+ return 927;
}
}
else
@@ -445,7 +445,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx110x00100x0
caspal. */
- return 990;
+ return 993;
}
else
{
@@ -453,7 +453,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx110x00100x1
ldaxp. */
- return 926;
+ return 929;
}
}
}
@@ -466,7 +466,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxx10x001010x
ldnp. */
- return 939;
+ return 942;
}
else
{
@@ -474,7 +474,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxx10x001011x
ldpsw. */
- return 946;
+ return 949;
}
}
}
@@ -494,7 +494,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx011x0010000
ldlarb. */
- return 933;
+ return 936;
}
else
{
@@ -502,7 +502,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx011x0010010
ldlarh. */
- return 934;
+ return 937;
}
}
else
@@ -511,7 +511,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx011x00100x1
ldlar. */
- return 932;
+ return 935;
}
}
else
@@ -524,7 +524,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx111x0010000
casab. */
- return 978;
+ return 981;
}
else
{
@@ -532,7 +532,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx111x0010010
casah. */
- return 981;
+ return 984;
}
}
else
@@ -541,7 +541,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx0xxxxx111x00100x1
casa. */
- return 984;
+ return 987;
}
}
}
@@ -557,7 +557,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx011x0010000
ldarb. */
- return 912;
+ return 915;
}
else
{
@@ -565,7 +565,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx011x0010010
ldarh. */
- return 918;
+ return 921;
}
}
else
@@ -574,7 +574,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx011x00100x1
ldar. */
- return 928;
+ return 931;
}
}
else
@@ -587,7 +587,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx111x0010000
casalb. */
- return 980;
+ return 983;
}
else
{
@@ -595,7 +595,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx111x0010010
casalh. */
- return 983;
+ return 986;
}
}
else
@@ -604,7 +604,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxx1xxxxx111x00100x1
casal. */
- return 986;
+ return 989;
}
}
}
@@ -617,7 +617,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxx11x001010x
ldp. */
- return 948;
+ return 951;
}
else
{
@@ -625,7 +625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxx11x001011x
ldpsw. */
- return 951;
+ return 954;
}
}
}
@@ -643,7 +643,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx000110x0
ldr. */
- return 952;
+ return 955;
}
else
{
@@ -653,7 +653,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx00011001
ldrsw. */
- return 954;
+ return 957;
}
else
{
@@ -661,7 +661,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx00011011
prfm. */
- return 955;
+ return 958;
}
}
}
@@ -685,7 +685,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx00xxxxxxxxx00000011100
sturb. */
- return 893;
+ return 896;
}
else
{
@@ -693,7 +693,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx00xxxxxxxxx00000011110
sturh. */
- return 898;
+ return 901;
}
}
else
@@ -702,7 +702,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx00xxxxxxxxx000000111x1
stur. */
- return 901;
+ return 904;
}
}
else
@@ -715,7 +715,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx00xxxxxxxxx01000011100
ldurb. */
- return 894;
+ return 897;
}
else
{
@@ -723,7 +723,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx00xxxxxxxxx01000011110
ldurh. */
- return 899;
+ return 902;
}
}
else
@@ -732,7 +732,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx00xxxxxxxxx010000111x1
ldur. */
- return 902;
+ return 905;
}
}
}
@@ -746,7 +746,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx00xxxxxxxxx0x100011100
ldursb. */
- return 895;
+ return 898;
}
else
{
@@ -754,7 +754,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx00xxxxxxxxx0x100011101
ldursw. */
- return 903;
+ return 906;
}
}
else
@@ -765,7 +765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx00xxxxxxxxx0x100011110
ldursh. */
- return 900;
+ return 903;
}
else
{
@@ -773,7 +773,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx00xxxxxxxxx0x100011111
prfum. */
- return 904;
+ return 907;
}
}
}
@@ -800,7 +800,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx10000011100
ldaddb. */
- return 1003;
+ return 1006;
}
else
{
@@ -808,7 +808,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx10000011110
ldaddh. */
- return 1004;
+ return 1007;
}
}
else
@@ -817,7 +817,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx100000111x1
ldadd. */
- return 1005;
+ return 1008;
}
}
else
@@ -830,7 +830,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx10100011100
ldaddab. */
- return 1006;
+ return 1009;
}
else
{
@@ -838,7 +838,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx10100011110
ldaddah. */
- return 1009;
+ return 1012;
}
}
else
@@ -847,7 +847,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx101000111x1
ldadda. */
- return 1012;
+ return 1015;
}
}
}
@@ -863,7 +863,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx11000011100
ldaddlb. */
- return 1007;
+ return 1010;
}
else
{
@@ -871,7 +871,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx11000011110
ldaddlh. */
- return 1010;
+ return 1013;
}
}
else
@@ -880,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx110000111x1
ldaddl. */
- return 1013;
+ return 1016;
}
}
else
@@ -893,7 +893,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx11100011100
ldaddalb. */
- return 1008;
+ return 1011;
}
else
{
@@ -901,7 +901,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx11100011110
ldaddalh. */
- return 1011;
+ return 1014;
}
}
else
@@ -910,7 +910,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000000xxxxx111000111x1
ldaddal. */
- return 1014;
+ return 1017;
}
}
}
@@ -929,7 +929,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx10000011100
swpb. */
- return 991;
+ return 994;
}
else
{
@@ -937,7 +937,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx10000011110
swph. */
- return 992;
+ return 995;
}
}
else
@@ -946,7 +946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx100000111x1
swp. */
- return 993;
+ return 996;
}
}
else
@@ -959,7 +959,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx10100011100
swpab. */
- return 994;
+ return 997;
}
else
{
@@ -967,7 +967,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx10100011110
swpah. */
- return 997;
+ return 1000;
}
}
else
@@ -976,7 +976,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx101000111x1
swpa. */
- return 1000;
+ return 1003;
}
}
}
@@ -992,7 +992,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx11000011100
swplb. */
- return 995;
+ return 998;
}
else
{
@@ -1000,7 +1000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx11000011110
swplh. */
- return 998;
+ return 1001;
}
}
else
@@ -1009,7 +1009,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx110000111x1
swpl. */
- return 1001;
+ return 1004;
}
}
else
@@ -1022,7 +1022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx11100011100
swpalb. */
- return 996;
+ return 999;
}
else
{
@@ -1030,7 +1030,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx11100011110
swpalh. */
- return 999;
+ return 1002;
}
}
else
@@ -1039,7 +1039,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000001xxxxx111000111x1
swpal. */
- return 1002;
+ return 1005;
}
}
}
@@ -1061,7 +1061,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000010xxxxx10000011100
ldsmaxb. */
- return 1051;
+ return 1054;
}
else
{
@@ -1069,7 +1069,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000010xxxxx10000011110
ldsmaxh. */
- return 1052;
+ return 1055;
}
}
else
@@ -1078,7 +1078,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxx000010xxxxx100[...]
[diff truncated at 100000 bytes]