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[binutils-gdb] Add support to AArch64 disassembler for verifying instructions. Add verifier for LDPSW.
- From: Nick Clifton <nickc at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 28 Apr 2016 08:12:17 -0000
- Subject: [binutils-gdb] Add support to AArch64 disassembler for verifying instructions. Add verifier for LDPSW.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=4bd13cde17a27c342b79b72bde9ef8e1b5373344
commit 4bd13cde17a27c342b79b72bde9ef8e1b5373344
Author: Nick Clifton <nickc@redhat.com>
Date: Thu Apr 28 09:11:03 2016 +0100
Add support to AArch64 disassembler for verifying instructions. Add verifier for LDPSW.
PR target/19722
opcodes * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
* aarch64-opc.c (verify_ldpsw): New function.
* aarch64-opc.h (verify_ldpsw): New prototype.
* aarch64-tbl.h: Add initialiser for verifier field.
(LDPSW): Set verifier to verify_ldpsw.
binutils* testsuite/binutils-all/aarch64/illegal.s: New test.
* testsuite/binutils-all/aarch64/illegal.d: New test driver.
include * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
Diff:
---
binutils/ChangeLog | 6 +
binutils/testsuite/binutils-all/aarch64/illegal.d | 12 +
binutils/testsuite/binutils-all/aarch64/illegal.s | 7 +
include/ChangeLog | 5 +
include/opcode/aarch64.h | 3 +
opcodes/ChangeLog | 9 +
opcodes/aarch64-dis.c | 8 +
opcodes/aarch64-opc.c | 28 +
opcodes/aarch64-opc.h | 3 +
opcodes/aarch64-tbl.h | 2523 ++++++++++-----------
10 files changed, 1272 insertions(+), 1332 deletions(-)
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 100ef0c..fc495cc 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,9 @@
+2016-04-28 Nick Clifton <nickc@redhat.com>
+
+ PR target/19722
+ * testsuite/binutils-all/aarch64/illegal.s: New test.
+ * testsuite/binutils-all/aarch64/illegal.d: New test driver.
+
2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* resres.c: Likewise.
diff --git a/binutils/testsuite/binutils-all/aarch64/illegal.d b/binutils/testsuite/binutils-all/aarch64/illegal.d
new file mode 100644
index 0000000..4b90a1d
--- /dev/null
+++ b/binutils/testsuite/binutils-all/aarch64/illegal.d
@@ -0,0 +1,12 @@
+#PROG: objcopy
+#objdump: -d
+#name: Check that the disassembler complains about illegal instructions.
+
+.*: +file format .*aarch64.*
+
+Disassembly of section \.text:
+
+0+000 <.*>:
+[ ]+0:[ ]+68ea18cc[ ]+.inst[ ]+0x68ea18cc ; undefined
+#pass
+
diff --git a/binutils/testsuite/binutils-all/aarch64/illegal.s b/binutils/testsuite/binutils-all/aarch64/illegal.s
new file mode 100644
index 0000000..216cbe6
--- /dev/null
+++ b/binutils/testsuite/binutils-all/aarch64/illegal.s
@@ -0,0 +1,7 @@
+ # Test disassembly of illegal instructions.
+ .text
+
+ # ldpsw x12, x6, [x6],#-8 ; illegal because one of the dest regs is also the address reg
+ .inst 0x68ea18cc
+
+ # FIXME: Add more illegal instructions here.
diff --git a/include/ChangeLog b/include/ChangeLog
index 1390d42..df2ebb3 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2016-04-28 Nick Clifton <nickc@redhat.com>
+
+ PR target/19722
+ * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
+
2016-04-27 Alan Modra <amodra@gmail.com>
* bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 3a28855..e6f080c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -535,6 +535,9 @@ struct aarch64_opcode
/* Flags providing information about this instruction */
uint32_t flags;
+
+ /* If non-NULL, a function to verify that a given instruction is valid. */
+ bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
};
typedef struct aarch64_opcode aarch64_opcode;
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b835086..a66e93f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2016-04-28 Nick Clifton <nickc@redhat.com>
+
+ PR target/19722
+ * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
+ * aarch64-opc.c (verify_ldpsw): New function.
+ * aarch64-opc.h (verify_ldpsw): New prototype.
+ * aarch64-tbl.h: Add initialiser for verifier field.
+ (LDPSW): Set verifier to verify_ldpsw.
+
2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/19983
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 05e4768..9ffc713 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2047,6 +2047,7 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
{
const aarch64_operand *opnd;
enum aarch64_opnd type;
+
type = opcode->operands[i];
if (type == AARCH64_OPND_NIL)
break;
@@ -2059,6 +2060,13 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
}
}
+ /* If the opcode has a verifier, then check it now. */
+ if (opcode->verifier && ! opcode->verifier (opcode, code))
+ {
+ DEBUG_TRACE ("operand verifier FAIL");
+ goto decode_fail;
+ }
+
/* Match the qualifiers. */
if (aarch64_match_operands_constraint (inst, NULL) == 1)
{
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 76992df..8fbea46 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3417,6 +3417,34 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
#undef C14
#undef C15
+#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
+#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
+
+bfd_boolean
+verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED,
+ const aarch64_insn insn)
+{
+ int t = BITS (insn, 4, 0);
+ int n = BITS (insn, 9, 5);
+ int t2 = BITS (insn, 14, 10);
+
+ if (BIT (insn, 23))
+ {
+ /* Write back enabled. */
+ if ((t == n || t2 == n) && n != 31)
+ return FALSE;
+ }
+
+ if (BIT (insn, 22))
+ {
+ /* Load */
+ if (t == t2)
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
/* Include the opcode description table as well as the operand description
table. */
#include "aarch64-tbl.h"
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 08494c6..c5bcbb8 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -390,4 +390,7 @@ get_logsz (unsigned int size)
return ls[size - 1];
}
+/* Instruction Verifiers. */
+extern bfd_boolean verify_ldpsw (const struct aarch64_opcode *, const aarch64_insn);
+
#endif /* OPCODES_AARCH64_OPC_H */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 872e3d1..7a47a17 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1374,1416 +1374,1275 @@ static const aarch64_feature_set aarch64_feature_simd_f16 =
static const aarch64_feature_set aarch64_feature_stat_profile =
AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0);
-#define CORE &aarch64_feature_v8
-#define FP &aarch64_feature_fp
-#define SIMD &aarch64_feature_simd
-#define CRYPTO &aarch64_feature_crypto
-#define CRC &aarch64_feature_crc
-#define LSE &aarch64_feature_lse
-#define LOR &aarch64_feature_lor
-#define RDMA &aarch64_feature_rdma
-#define FP_F16 &aarch64_feature_fp_f16
+#define CORE &aarch64_feature_v8
+#define FP &aarch64_feature_fp
+#define SIMD &aarch64_feature_simd
+#define CRYPTO &aarch64_feature_crypto
+#define CRC &aarch64_feature_crc
+#define LSE &aarch64_feature_lse
+#define LOR &aarch64_feature_lor
+#define RDMA &aarch64_feature_rdma
+#define FP_F16 &aarch64_feature_fp_f16
#define SIMD_F16 &aarch64_feature_simd_f16
-#define RAS &aarch64_feature_ras
+#define RAS &aarch64_feature_ras
#define STAT_PROFILE &aarch64_feature_stat_profile
-#define ARMV8_2 &aarch64_feature_v8_2
+#define ARMV8_2 &aarch64_feature_v8_2
+
+#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, CORE, OPS, QUALS, FLAGS, NULL }
+#define __FP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP, OPS, QUALS, FLAGS, NULL }
+#define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, SIMD, OPS, QUALS, FLAGS, NULL }
+#define CRYP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, CRYPTO, OPS, QUALS, FLAGS, NULL }
+#define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, NULL }
+#define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, NULL }
+#define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, NULL }
+#define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, NULL }
+#define FF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, NULL }
+#define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, NULL }
struct aarch64_opcode aarch64_opcode_table[] =
{
/* Add/subtract (with carry). */
- {"adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
- {"adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
- {"sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
- {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
- {"sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
- {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
+ CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+ CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+ CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
+ CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
+ CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
+ CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
/* Add/subtract (extended register). */
- {"add", 0x0b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
- {"adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
- {"cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
- {"sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
- {"subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
- {"cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
+ CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
+ CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
+ CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
+ CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
+ CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
+ CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF),
/* Add/subtract (immediate). */
- {"add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
- {"mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, CORE, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF},
- {"adds", 0x31000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
- {"cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
- {"sub", 0x51000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF},
- {"subs", 0x71000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
- {"cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
+ { "add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF, NULL},
+ CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF),
+ CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
+ CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
+ CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
+ CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
+ CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
/* Add/subtract (shifted register). */
- {"add", 0xb000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
- {"adds", 0x2b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
- {"cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
- {"sub", 0x4b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
- {"neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
- {"subs", 0x6b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
- {"cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
- {"negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
+ CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
+ CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
+ CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
+ CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
+ CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
+ CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
+ CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
+ CORE_INSN ("negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
/* AdvSIMD across lanes. */
- {"saddlv", 0xe303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ},
- {"smaxv", 0xe30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
- {"sminv", 0xe31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
- {"addv", 0xe31b800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
- {"uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ},
- {"umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
- {"uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
- {"fmaxnmv", 0x2e30c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
- {"fmaxnmv", 0xe30c800, 0xbffffc00, asimdall, 0, SIMD_F16,
- OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
- {"fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
- {"fmaxv", 0xe30f800, 0xbffffc00, asimdall, 0, SIMD_F16,
- OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
- {"fminnmv", 0x2eb0c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
- {"fminnmv", 0xeb0c800, 0xbffffc00, asimdall, 0, SIMD_F16,
- OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
- {"fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
- {"fminv", 0xeb0f800, 0xbffffc00, asimdall, 0, SIMD_F16,
- OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
+ SIMD_INSN ("saddlv", 0x0e303800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ),
+ SIMD_INSN ("smaxv", 0x0e30a800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ),
+ SIMD_INSN ("sminv", 0x0e31a800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ),
+ SIMD_INSN ("addv", 0x0e31b800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ),
+ SIMD_INSN ("uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ),
+ SIMD_INSN ("umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ),
+ SIMD_INSN ("uminv", 0x2e31a800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ),
+ SIMD_INSN ("fmaxnmv",0x2e30c800, 0xbfbffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ),
+ SF16_INSN ("fmaxnmv",0x0e30c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ),
+ SIMD_INSN ("fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ),
+ SF16_INSN ("fmaxv", 0x0e30f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ),
+ SIMD_INSN ("fminnmv",0x2eb0c800, 0xbfbffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ),
+ SF16_INSN ("fminnmv",0x0eb0c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ),
+ SIMD_INSN ("fminv", 0x2eb0f800, 0xbfbffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ),
+ SF16_INSN ("fminv", 0x0eb0f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ),
/* AdvSIMD three different. */
- {"saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
- {"saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
- {"ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
- {"ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
- {"addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
- {"addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
- {"sabal", 0x0e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"sabal2", 0x4e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"subhn", 0x0e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
- {"subhn2", 0x4e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
- {"sabdl", 0x0e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"sabdl2", 0x4e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"smlal", 0x0e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"smlal2", 0x4e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
- {"sqdmlal2", 0x4e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
- {"smlsl", 0x0e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
- {"sqdmlsl2", 0x4e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
- {"smull", 0x0e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"smull2", 0x4e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
- {"sqdmull2", 0x4e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
- {"pmull", 0x0e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0},
- {"pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0},
- {"pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0},
- {"pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0},
- {"uaddl", 0x2e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"uaddl2", 0x6e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"uaddw", 0x2e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
- {"uaddw2", 0x6e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
- {"usubl", 0x2e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"usubl2", 0x6e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"usubw", 0x2e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
- {"usubw2", 0x6e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
- {"raddhn", 0x2e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
- {"raddhn2", 0x6e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
- {"uabal", 0x2e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"uabal2", 0x6e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
- {"rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
- {"uabdl", 0x2e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"uabdl2", 0x6e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"umlal", 0x2e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"umlal2", 0x6e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"umlsl", 0x2e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
- {"umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
- {"umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
+ SIMD_INSN ("saddl", 0x0e200000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("saddl2", 0x4e200000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("saddw", 0x0e201000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ),
+ SIMD_INSN ("saddw2", 0x4e201000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ),
+ SIMD_INSN ("ssubl", 0x0e202000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("ssubl2", 0x4e202000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("ssubw", 0x0e203000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ),
+ SIMD_INSN ("ssubw2", 0x4e203000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ),
+ SIMD_INSN ("addhn", 0x0e204000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ),
+ SIMD_INSN ("addhn2", 0x4e204000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ),
+ SIMD_INSN ("sabal", 0x0e205000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("sabal2", 0x4e205000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("subhn", 0x0e206000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ),
+ SIMD_INSN ("subhn2", 0x4e206000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ),
+ SIMD_INSN ("sabdl", 0x0e207000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("sabdl2", 0x4e207000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("smlal", 0x0e208000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("smlal2", 0x4e208000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ),
+ SIMD_INSN ("sqdmlal2",0x4e209000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ),
+ SIMD_INSN ("smlsl", 0x0e20a000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ),
+ SIMD_INSN ("sqdmlsl2",0x4e20b000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ),
+ SIMD_INSN ("smull", 0x0e20c000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("smull2", 0x4e20c000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ),
+ SIMD_INSN ("sqdmull2",0x4e20d000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ),
+ SIMD_INSN ("pmull", 0x0e20e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0),
+ CRYP_INSN ("pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0),
+ SIMD_INSN ("pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0),
+ CRYP_INSN ("pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0),
+ SIMD_INSN ("uaddl", 0x2e200000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("uaddl2", 0x6e200000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("uaddw", 0x2e201000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ),
+ SIMD_INSN ("uaddw2", 0x6e201000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ),
+ SIMD_INSN ("usubl", 0x2e202000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("usubl2", 0x6e202000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("usubw", 0x2e203000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ),
+ SIMD_INSN ("usubw2", 0x6e203000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ),
+ SIMD_INSN ("raddhn", 0x2e204000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ),
+ SIMD_INSN ("raddhn2", 0x6e204000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ),
+ SIMD_INSN ("uabal", 0x2e205000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("uabal2", 0x6e205000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("rsubhn", 0x2e206000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ),
+ SIMD_INSN ("rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ),
+ SIMD_INSN ("uabdl", 0x2e207000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("uabdl2", 0x6e207000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("umlal", 0x2e208000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("umlal2", 0x6e208000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("umlsl", 0x2e20a000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("umull", 0x2e20c000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
+ SIMD_INSN ("umull2", 0x6e20c000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
/* AdvSIMD vector x indexed element. */
- {"smlal", 0x0f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
- {"smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
- {"sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
- {"sqdmlal2", 0x4f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
- {"smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
- {"smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
- {"sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
- {"sqdmlsl2", 0x4f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
- {"mul", 0xf008000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
- {"smull", 0x0f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
- {"smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
- {"sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
- {"sqdmull2", 0x4f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
- {"sqdmulh", 0xf00c000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
- {"sqrdmulh", 0xf00d000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
- {"fmla", 0xf801000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
- {"fmla", 0xf001000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
- OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
- {"fmls", 0xf805000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
- {"fmls", 0xf005000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
- OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
- {"fmul", 0xf809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
- {"fmul", 0xf009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
- OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
- {"mla", 0x2f000000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
- {"umlal", 0x2f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
- {"umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
- {"mls", 0x2f004000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
- {"umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
- {"umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
- {"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
- {"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
- {"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
- {"fmulx", 0x2f009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
- OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
- {"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
- {"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
+ SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
+ SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
+ SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
+ SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
+ SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
+ SIMD_INSN ("smlsl2", 0x4f006000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
+ SIMD_INSN ("sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
+ SIMD_INSN ("sqdmlsl2",0x4f007000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
+ SIMD_INSN ("mul", 0x0f008000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
+ SIMD_INSN ("smull", 0x0f00a000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
+ SIMD_INSN ("smull2", 0x4f00a000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
+ SIMD_INSN ("sqdmull", 0x0f00b000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
+ SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
+ SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
+ SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
+ SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
+ SF16_INSN ("fmla", 0x0f001000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ),
+ SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
+ SF16_INSN ("fmls", 0x0f005000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ),
+ SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
+ SF16_INSN ("fmul", 0x0f009000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ),
+ SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
+ SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
+ SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
+ SIMD_INSN ("mls", 0x2f004000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
+ SIMD_INSN ("umlsl", 0x2f006000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
+ SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
+ SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
+ SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
+ SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
+ SF16_INSN ("fmulx", 0x2f009000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ),
+ RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
+ RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
/* AdvSIMD EXT. */
- {"ext", 0x2e000000, 0xbfe08400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
+ SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ),
/* AdvSIMD modified immediate. */
- {"movi", 0xf000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
- {"orr", 0xf001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
- {"movi", 0xf008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
- {"orr", 0xf009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
- {"movi", 0xf00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
- {"movi", 0xf00e400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ},
- {"fmov", 0xf00f400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ},
- {"fmov", 0xf00fc00, 0xbff8fc00, asimdimm, 0, SIMD_F16,
- OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_H, F_SIZEQ},
- {"mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
- {"bic", 0x2f001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
- {"mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
- {"bic", 0x2f009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
- {"mvni", 0x2f00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
- {"movi", 0x2f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ},
- {"movi", 0x6f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ},
- {"fmov", 0x6f00f400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ},
+ SIMD_INSN ("movi", 0x0f000400, 0xbff89c00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ),
+ SIMD_INSN ("orr", 0x0f001400, 0xbff89c00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ),
+ SIMD_INSN ("movi", 0x0f008400, 0xbff8dc00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ),
+ SIMD_INSN ("orr", 0x0f009400, 0xbff8dc00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ),
+ SIMD_INSN ("movi", 0x0f00c400, 0xbff8ec00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ),
+ SIMD_INSN ("movi", 0x0f00e400, 0xbff8fc00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ),
+ SIMD_INSN ("fmov", 0x0f00f400, 0xbff8fc00, asimdimm, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ),
+ SF16_INSN ("fmov", 0x0f00fc00, 0xbff8fc00, asimdimm, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_H, F_SIZEQ),
+ SIMD_INSN ("mvni", 0x2f000400, 0xbff89c00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ),
+ SIMD_INSN ("bic", 0x2f001400, 0xbff89c00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ),
+ SIMD_INSN ("mvni", 0x2f008400, 0xbff8dc00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ),
+ SIMD_INSN ("bic", 0x2f009400, 0xbff8dc00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ),
+ SIMD_INSN ("mvni", 0x2f00c400, 0xbff8ec00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ),
+ SIMD_INSN ("movi", 0x2f00e400, 0xfff8fc00, asimdimm, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ),
+ SIMD_INSN ("movi", 0x6f00e400, 0xfff8fc00, asimdimm, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ),
+ SIMD_INSN ("fmov", 0x6f00f400, 0xfff8fc00, asimdimm, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ),
/* AdvSIMD copy. */
- {"dup", 0xe000400, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, En), QL_DUP_VX, F_T},
- {"dup", 0xe000c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, Rn), QL_DUP_VR, F_T},
- {"smov", 0xe002c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q},
- {"umov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q},
- {"mov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q},
- {"ins", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS},
- {"mov", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS},
- {"ins", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS},
- {"mov", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_ALIAS},
+ SIMD_INSN ("dup", 0x0e000400, 0xbfe0fc00, asimdins, OP2 (Vd, En), QL_DUP_VX, F_T),
+ SIMD_INSN ("dup", 0x0e000c00, 0xbfe0fc00, asimdins, OP2 (Vd, Rn), QL_DUP_VR, F_T),
+ SIMD_INSN ("smov",0x0e002c00, 0xbfe0fc00, asimdins, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q),
+ SIMD_INSN ("umov",0x0e003c00, 0xbfe0fc00, asimdins, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q),
+ SIMD_INSN ("mov", 0x0e003c00, 0xbfe0fc00, asimdins, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q),
+ SIMD_INSN ("ins", 0x4e001c00, 0xffe0fc00, asimdins, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS),
+ SIMD_INSN ("mov", 0x4e001c00, 0xffe0fc00, asimdins, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS),
+ SIMD_INSN ("ins", 0x6e000400, 0xffe08400, asimdins, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS),
+ SIMD_INSN ("mov", 0x6e000400, 0xffe08400, asimdins, OP2 (Ed, En), QL_S_2SAME, F_ALIAS),
/* AdvSIMD two-reg misc. */
- {"rev64", 0xe200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
- {"rev16", 0xe201800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
- {"saddlp", 0xe202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
- {"suqadd", 0xe203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
- {"cls", 0xe204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
- {"cnt", 0xe205800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
- {"sadalp", 0xe206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
- {"sqabs", 0xe207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
- {"cmgt", 0xe208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
- {"cmeq", 0xe209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
- {"cmlt", 0xe20a800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
- {"abs", 0xe20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
- {"xtn", 0xe212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
- {"xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
- {"sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
- {"sqxtn2", 0x4e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
- {"fcvtn", 0xe216800, 0xffbffc00, asimdmisc, OP_FCVTN, SIMD, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC},
- {"fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, SIMD, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC},
- {"fcvtl", 0xe217800, 0xffbffc00, asimdmisc, OP_FCVTL, SIMD, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC},
- {"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC},
- {"frintn", 0xe218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"frintn", 0xe798800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"frintm", 0xe219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"frintm", 0xe799800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcvtns", 0xe21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fcvtns", 0xe79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcvtms", 0xe21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fcvtms", 0xe79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcvtas", 0xe21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fcvtas", 0xe79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"scvtf", 0xe21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"scvtf", 0xe79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
- {"fcmgt", 0xef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
- {"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
- {"fcmeq", 0xef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
- {"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
- {"fcmlt", 0xef8e800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
- {"fabs", 0xea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fabs", 0xef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"frintp", 0xea18800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"frintp", 0xef98800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"frintz", 0xea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"frintz", 0xef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcvtps", 0xea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fcvtps", 0xef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcvtzs", 0xea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fcvtzs", 0xef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"urecpe", 0xea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
- {"frecpe", 0xea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"frecpe", 0xef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ},
- {"uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
- {"usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
- {"clz", 0x2e204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
- {"uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
- {"sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
- {"cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
- {"cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
- {"neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
- {"sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
- {"sqxtun2", 0x6e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
- {"shll", 0x2e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ},
- {"shll2", 0x6e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ},
- {"uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
- {"uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
- {"fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS, 0},
- {"fcvtxn2", 0x6e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS2, 0},
- {"frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"frinta", 0x2e798800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"frintx", 0x2e799800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"not", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS},
- {"mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS},
- {"rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
- {"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
- {"fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
- {"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
- {"fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
- {"fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"frinti", 0x2ef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"ursqrte", 0x2ea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
- {"frsqrte", 0x2ea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"frsqrte", 0x2ef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
- {"fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
- {"fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
- OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
+ SIMD_INSN ("rev64", 0x0e200800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("rev16", 0x0e201800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ),
+ SIMD_INSN ("saddlp",0x0e202800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ),
+ SIMD_INSN ("suqadd",0x0e203800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("cls", 0x0e204800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("cnt", 0x0e205800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ),
+ SIMD_INSN ("sadalp",0x0e206800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ),
+ SIMD_INSN ("sqabs", 0x0e207800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("cmgt", 0x0e208800, 0xbf3ffc00, asimdmisc, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("cmeq", 0x0e209800, 0xbf3ffc00, asimdmisc, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("cmlt", 0x0e20a800, 0xbf3ffc00, asimdmisc, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("abs", 0x0e20b800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("xtn", 0x0e212800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ),
+ SIMD_INSN ("xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ),
+ SIMD_INSN ("sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ),
+ SIMD_INSN ("sqxtn2",0x4e214800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ),
+ {"fcvtn", 0x0e216800, 0xffbffc00, asimdmisc, OP_FCVTN, SIMD, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC, NULL},
+ {"fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, SIMD, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC, NULL},
+ {"fcvtl", 0x0e217800, 0xffbffc00, asimdmisc, OP_FCVTL, SIMD, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC, NULL},
+ {"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC, NULL},
+ SIMD_INSN ("frintn", 0x0e218800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("frintn", 0x0e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("frintm", 0x0e219800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("frintm", 0x0e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcvtns", 0x0e21a800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcvtns", 0x0e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcvtms", 0x0e21b800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcvtms", 0x0e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcvtas", 0x0e21c800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcvtas", 0x0e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("scvtf", 0x0e21d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("scvtf", 0x0e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcmgt", 0x0ea0c800, 0xbfbffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcmgt", 0x0ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcmeq", 0x0ea0d800, 0xbfbffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcmeq", 0x0ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcmlt", 0x0ea0e800, 0xbfbffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcmlt", 0x0ef8e800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fabs", 0x0ea0f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fabs", 0x0ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("frintp", 0x0ea18800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("frintp", 0x0ef98800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("frintz", 0x0ea19800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("frintz", 0x0ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcvtps", 0x0ea1a800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcvtps", 0x0ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcvtzs", 0x0ea1b800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcvtzs", 0x0ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("urecpe", 0x0ea1c800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ),
+ SIMD_INSN ("frecpe", 0x0ea1d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("frecpe", 0x0ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ),
+ SIMD_INSN ("uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ),
+ SIMD_INSN ("usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("clz", 0x2e204800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ),
+ SIMD_INSN ("sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ),
+ SIMD_INSN ("sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ),
+ SIMD_INSN ("sqxtun2",0x6e212800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ),
+ SIMD_INSN ("shll", 0x2e213800, 0xff3ffc00, asimdmisc, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ),
+ SIMD_INSN ("shll2", 0x6e213800, 0xff3ffc00, asimdmisc, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ),
+ SIMD_INSN ("uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ),
+ SIMD_INSN ("uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ),
+ SIMD_INSN ("fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRS, 0),
+ SIMD_INSN ("fcvtxn2",0x6e616800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRS2, 0),
+ SIMD_INSN ("frinta", 0x2e218800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("frinta", 0x2e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("frintx", 0x2e219800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("frintx", 0x2e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("not", 0x2e205800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS),
+ SIMD_INSN ("mvn", 0x2e205800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS),
+ SIMD_INSN ("rbit", 0x2e605800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ),
+ SIMD_INSN ("fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("frinti", 0x2ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("ursqrte",0x2ea1c800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ),
+ SIMD_INSN ("frsqrte",0x2ea1d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("frsqrte",0x2ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
+ SIMD_INSN ("fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
+ SF16_INSN ("fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ),
/* AdvSIMD ZIP/UZP/TRN. */
- {"uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"zip1", 0xe003800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"uzp2", 0xe005800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"trn2", 0xe006800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"zip2", 0xe007800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
+ SIMD_INSN ("uzp1", 0xe001800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("trn1", 0xe002800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("zip1", 0xe003800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("uzp2", 0xe005800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("trn2", 0xe006800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("zip2", 0xe007800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
/* AdvSIMD three same. */
- {"shadd", 0xe200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"sqadd", 0xe200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"srhadd", 0xe201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"shsub", 0xe202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"sqsub", 0xe202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"cmgt", 0xe203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"cmge", 0xe203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"sshl", 0xe204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"sqshl", 0xe204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"srshl", 0xe205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"smax", 0xe206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"smin", 0xe206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"sabd", 0xe207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"saba", 0xe207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"add", 0xe208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"cmtst", 0xe208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"mla", 0xe209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"mul", 0xe209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"smaxp", 0xe20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"sminp", 0xe20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
- {"addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fmla", 0xe400c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fadd", 0xe401400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fmax", 0xe403400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"frecps", 0xe403c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
- {"bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
- {"fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fminnm", 0xec00400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fmls", 0xec00c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fsub", 0xec01400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fmin", 0xec03400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ},
- {"mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV},
- {"orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
- {"uhadd", 0x2e200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"urhadd", 0x2e201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"uhsub", 0x2e202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"cmhi", 0x2e203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"ushl", 0x2e204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"urshl", 0x2e205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"umax", 0x2e206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"umin", 0x2e206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"uabd", 0x2e207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"uaba", 0x2e207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"sub", 0x2e208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
- {"mls", 0x2e209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"pmul", 0x2e209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
- {"umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
- {"sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
- {"fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"faddp", 0x2e401400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"facge", 0x2e402c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
- {"bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
- {"fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
- {"fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
- OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
- {"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
- {"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ SIMD_INSN ("shadd", 0xe200400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("sqadd", 0xe200c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("srhadd", 0xe201400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("shsub", 0xe202400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("sqsub", 0xe202c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("cmgt", 0xe203400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("cmge", 0xe203c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("sshl", 0xe204400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("sqshl", 0xe204c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("srshl", 0xe205400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("smax", 0xe206400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("smin", 0xe206c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("sabd", 0xe207400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("saba", 0xe207c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("add", 0xe208400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("cmtst", 0xe208c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("mla", 0xe209400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("mul", 0xe209c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("smaxp", 0xe20a400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("sminp", 0xe20ac00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
+ SIMD_INSN ("addp", 0xe20bc00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fmla", 0xe400c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fadd", 0xe20d400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fadd", 0xe401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fmax", 0xe20f400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fmax", 0xe403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("frecps", 0xe403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("and", 0xe201c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
+ SIMD_INSN ("bic", 0xe601c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
+ SIMD_INSN ("fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fminnm", 0xec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fmls", 0xec00c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fsub", 0xea0d400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fsub", 0xec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fmin", 0xea0f400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fmin", 0xec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("orr", 0xea01c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ),
+ {"mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV, NULL},
+ SIMD_INSN ("orn", 0xee01c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
+ SIMD_INSN ("uhadd", 0x2e200400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("urhadd", 0x2e201400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("uhsub", 0x2e202400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("cmhi", 0x2e203400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("ushl", 0x2e204400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("urshl", 0x2e205400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("umax", 0x2e206400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("umin", 0x2e206c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("uabd", 0x2e207400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("uaba", 0x2e207c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("sub", 0x2e208400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ),
+ SIMD_INSN ("mls", 0x2e209400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("pmul", 0x2e209c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
+ SIMD_INSN ("umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ),
+ SIMD_INSN ("sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
+ SIMD_INSN ("fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("faddp", 0x2e401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("facge", 0x2e402c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("eor", 0x2e201c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
+ SIMD_INSN ("bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
+ SIMD_INSN ("fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ SF16_INSN ("fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ),
+ SIMD_INSN ("bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
+ SIMD_INSN ("bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
/* AdvSIMD three same extension. */
- {"sqrdmlah", 0x2e008400, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
- {"sqrdmlsh", 0x2e008c00, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
+ RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
+ RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
/* AdvSIMD shift by immediate. */
- {"sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
- {"ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
- {"srshr", 0xf002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
- {"srsra", 0xf003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
- {"shl", 0xf005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
- {"sqshl", 0xf007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
- {"shrn", 0xf008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
- {"shrn2", 0x4f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
- {"rshrn", 0xf008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
- {"rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
- {"sqshrn", 0xf009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
- {"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
- {"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
- {"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
- {"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
- {"sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
- {"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
- {"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
- {"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
- {"scvtf", 0xf10e400, 0xbf80fc00, asimdshf, 0, SIMD_F16,
- OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0},
- {"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
- {"fcvtzs", 0xf10fc00, 0xbf80fc00, asimdshf, 0, SIMD_F16,
- OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0},
- {"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
- {"usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
- {"urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
- {"ursra", 0x2f003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
- {"sri", 0x2f004400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
- {"sli", 0x2f005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
- {"sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
- {"uqshl", 0x2f007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
- {"sqshrun", 0x2f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
- {"sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
- {"sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
- {"sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
- {"uqshrn", 0x2f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
- {"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
- {"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
- {"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
- {"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
- {"uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
- {"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
- {"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
- {"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
- {"ucvtf", 0x2f10e400, 0xbf80fc00, asimdshf, 0, SIMD_F16,
- OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0},
- {"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
- {"fcvtzu", 0x2f10fc00, 0xbf80fc00, asimdshf, 0, SIMD_F16,
- OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0},
+ SIMD_INSN ("sshr", 0xf000400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
+ SIMD_INSN ("ssra", 0xf001400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
+ SIMD_INSN ("srshr", 0xf002400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
+ SIMD_INSN ("srsra", 0xf003400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
+ SIMD_INSN ("shl", 0xf005400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0),
+ SIMD_INSN ("sqshl", 0xf007400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0),
+ SIMD_INSN ("shrn", 0xf008400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0),
+ SIMD_INSN ("shrn2", 0x4f008400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0),
+ SIMD_INSN ("rshrn", 0xf008c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0),
+ SIMD_INSN ("rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0),
+ SIMD_INSN ("sqshrn", 0xf009400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0),
+ SIMD_INSN ("sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0),
+ SIMD_INSN ("sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0),
+ SIMD_INSN ("sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0),
+ SIMD_INSN ("sshll", 0xf00a400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS),
+ {"sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV, NULL},
+ SIMD_INSN ("sshll2", 0x4f00a400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS),
+ {"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV, NULL},
+ SIMD_INSN ("scvtf", 0xf00e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0),
+ SF16_INSN ("scvtf", 0xf10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0),
+ SIMD_INSN ("fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0),
+ SF16_INSN ("fcvtzs", 0xf10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0),
+ SIMD_INSN ("ushr", 0x2f000400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
+ SIMD_INSN ("usra", 0x2f001400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
+ SIMD_INSN ("urshr", 0x2f002400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
+ SIMD_INSN ("ursra", 0x2f003400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
+ SIMD_INSN ("sri", 0x2f004400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0),
+ SIMD_INSN ("sli", 0x2f005400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0),
+ SIMD_INSN ("sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0),
+ SIMD_INSN ("uqshl", 0x2f007400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0),
+ SIMD_INSN ("sqshrun", 0x2f008400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0),
+ SIMD_INSN ("sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0),
+ SIMD_INSN ("sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0),
+ SIMD_INSN ("sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0),
+ SIMD_INSN ("uqshrn", 0x2f009400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0),
+ SIMD_INSN ("uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0),
+ SIMD_INSN ("uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0),
+ SIMD_INSN ("uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0),
+ SIMD_INSN ("ushll", 0x2f00a400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS),
+ {"uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV, NULL},
+ SIMD_INSN ("ushll2", 0x6f00a400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS),
+ {"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV, NULL},
+ SIMD_INSN ("ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0),
+ SF16_INSN ("ucvtf", 0x2f10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0),
+ SIMD_INSN ("fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0),
+ SF16_INSN ("fcvtzu", 0x2f10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0),
/* AdvSIMD TBL/TBX. */
- {"tbl", 0xe000000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ},
- {"tbx", 0xe001000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ},
+ SIMD_INSN ("tbl", 0xe000000, 0xbfe09c00, asimdtbl, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ),
+ SIMD_INSN ("tbx", 0xe001000, 0xbfe09c00, asimdtbl, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ),
/* AdvSIMD scalar three different. */
- {"sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
- {"sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
- {"sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
+ SIMD_INSN ("sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE),
+ SIMD_INSN ("sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE),
+ SIMD_INSN ("sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE),
/* AdvSIMD scalar x indexed element. */
- {"sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
- {"sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
- {"sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
- {"sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
- {"sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
- {"fmla", 0x5f801000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
- {"fmla", 0x5f001000, 0xffc0f400, asisdelem, 0, SIMD_F16,
- OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
- {"fmls", 0x5f805000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
- {"fmls", 0x5f005000, 0xffc0f400, asisdelem, 0, SIMD_F16,
- OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
- {"fmul", 0x5f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
- {"fmul", 0x5f009000, 0xffc0f400, asisdelem, 0, SIMD_F16,
- OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
- {"fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
- {"fmulx", 0x7f009000, 0xffc0f400, asisdelem, 0, SIMD_F16,
- OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
- {"sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
- {"sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
+ SIMD_INSN ("sqdmlal", 0x5f003000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE),
+ SIMD_INSN ("sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE),
+ SIMD_INSN ("sqdmull", 0x5f00b000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE),
+ SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE),
+ SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE),
+ SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
+ SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE),
+ SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
+ SF16_INSN ("fmls", 0x5f005000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE),
+ SIMD_INSN ("fmul", 0x5f809000, 0xff80f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
+ SF16_INSN ("fmul", 0x5f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE),
+ SIMD_INSN ("fmulx", 0x7f809000, 0xff80f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
+ SF16_INSN ("fmulx", 0x7f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE),
+ RDMA_INSN ("sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE),
+ RDMA_INSN ("sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE),
/* AdvSIMD load/store multiple structures. */
- {"st4", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
- {"st1", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
- {"st2", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
- {"st3", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
- {"ld4", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
- {"ld1", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
- {"ld2", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
- {"ld3", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
+ SIMD_INSN ("st4", 0xc000000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)),
+ SIMD_INSN ("st1", 0xc000000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)),
+ SIMD_INSN ("st2", 0xc000000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)),
+ SIMD_INSN ("st3", 0xc000000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)),
+ SIMD_INSN ("ld4", 0xc400000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)),
+ SIMD_INSN ("ld1", 0xc400000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)),
+ SIMD_INSN ("ld2", 0xc400000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)),
+ SIMD_INSN ("ld3", 0xc400000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)),
/* AdvSIMD load/store multiple structures (post-indexed). */
- {"st4", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
- {"st1", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
- {"st2", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
- {"st3", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
- {"ld4", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
- {"ld1", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
- {"ld2", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
- {"ld3", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
+ SIMD_INSN ("st4", 0xc800000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)),
+ SIMD_INSN ("st1", 0xc800000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)),
+ SIMD_INSN ("st2", 0xc800000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)),
+ SIMD_INSN ("st3", 0xc800000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)),
+ SIMD_INSN ("ld4", 0xcc00000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)),
+ SIMD_INSN ("ld1", 0xcc00000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)),
+ SIMD_INSN ("ld2", 0xcc00000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)),
+ SIMD_INSN ("ld3", 0xcc00000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)),
/* AdvSIMD load/store single structure. */
- {"st1", 0xd000000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)},
- {"st3", 0xd002000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)},
- {"st2", 0xd200000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)},
- {"st4", 0xd202000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)},
- {"ld1", 0xd400000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)},
- {"ld3", 0xd402000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)},
- {"ld1r", 0xd40c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
- {"ld3r", 0xd40e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)},
- {"ld2", 0xd600000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)},
- {"ld4", 0xd602000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)},
- {"ld2r", 0xd60c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)},
- {"ld4r", 0xd60e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 ([...]
[diff truncated at 100000 bytes]