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[binutils-gdb/binutils-2_26-branch] Enable 2 operand form of powerpc mfcr with -many
- From: Alan Modra <amodra at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 26 Feb 2016 13:07:16 -0000
- Subject: [binutils-gdb/binutils-2_26-branch] Enable 2 operand form of powerpc mfcr with -many
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=239803398de94a92fdcef24b5d7914842dcc5797
commit 239803398de94a92fdcef24b5d7914842dcc5797
Author: Alan Modra <amodra@gmail.com>
Date: Fri Feb 26 23:35:13 2016 +1030
Enable 2 operand form of powerpc mfcr with -many
This is a workaround for a gcc bug.
PR 19359
* ppc-opc.c (insert_fxm): Remove "ignored" from error message.
(powerpc_opcodes): Remove single-operand mfcr.
Diff:
---
opcodes/ChangeLog | 8 ++++++++
opcodes/ppc-opc.c | 5 ++---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4582238..e7f539a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2016-02-26 Alan Modra <amodra@gmail.com>
+
+ Apply from master.
+ 2015-12-12 Alan Modra <amodra@gmail.com>
+ PR 19359
+ * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
+ (powerpc_opcodes): Remove single-operand mfcr.
+
2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
Backport from master
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index e8c92f6..9b25b60 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1434,7 +1434,7 @@ insert_fxm (unsigned long insn,
/* A value of -1 means we used the one operand form of
mfcr which is valid. */
if (value != -1)
- *errmsg = _("ignoring invalid mfcr mask");
+ *errmsg = _("invalid mfcr mask");
value = 0;
}
@@ -4742,8 +4742,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}},
{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}},
-{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
-{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4, {RT}},
+{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM4}},
{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM}},
{"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},