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[binutils-gdb/binutils-2_26-branch] [AArch64][PATCH 2/2] Add RAS system registers.
- From: Matthew Wahab <mwahab at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 14 Dec 2015 13:50:22 -0000
- Subject: [binutils-gdb/binutils-2_26-branch] [AArch64][PATCH 2/2] Add RAS system registers.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=eb763e171a6ae665e8dcdae576667e175d1afb70
commit eb763e171a6ae665e8dcdae576667e175d1afb70
Author: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu Dec 10 14:09:03 2015 +0000
[AArch64][PATCH 2/2] Add RAS system registers.
The ARMv8.2 RAS extension adds a number of new registers. This patch
adds the registers and makes them available whenever the RAS extension
is enabled, as it is when -march=armv8.2-a is selected.
The new registers are:
erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1,
erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and
vdisr_el2.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for new registers.
* gas/aarch64/sysreg-2.s: Likewise. Also replace some spaces with
tabs.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
"errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
"erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
(aarch64_sys_reg_supported_p): Add architecture feature tests for
new registers.
Change-Id: I8a01a0f0ee7987f89eead32650f6afcc749b3c74
Diff:
---
gas/testsuite/ChangeLog | 6 ++++++
gas/testsuite/gas/aarch64/sysreg-2.d | 18 ++++++++++++++++++
gas/testsuite/gas/aarch64/sysreg-2.s | 17 +++++++++++++++++
opcodes/ChangeLog | 8 ++++++++
opcodes/aarch64-opc.c | 37 ++++++++++++++++++++++++++++++++++++
5 files changed, 86 insertions(+)
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 3929849..f21957f 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,11 @@
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+ * gas/aarch64/sysreg-2.d: Add tests for new registers.
+ * gas/aarch64/sysreg-2.s: Likewise. Also replace some spaces with
+ tabs.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
* gas/aarch64/system-2.d: New.
* gas/aarch64/system-2.s: New.
* gas/aarch64/system.d: Adjust expected output for HINT 16.
diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d
index f0fe533..31b9f33 100644
--- a/gas/testsuite/gas/aarch64/sysreg-2.d
+++ b/gas/testsuite/gas/aarch64/sysreg-2.d
@@ -9,3 +9,21 @@ Disassembly of section .text:
0000000000000000 <.*>:
[0-9a-f]+: d5380725 mrs x5, id_aa64mmfr1_el1
[0-9a-f]+: d5380747 mrs x7, id_aa64mmfr2_el1
+ [0-9a-f]+: d5385305 mrs x5, erridr_el1
+ [0-9a-f]+: d5185327 msr errselr_el1, x7
+ [0-9a-f]+: d5385327 mrs x7, errselr_el1
+ [0-9a-f]+: d5385405 mrs x5, erxfr_el1
+ [0-9a-f]+: d5185425 msr erxctlr_el1, x5
+ [0-9a-f]+: d5385425 mrs x5, erxctlr_el1
+ [0-9a-f]+: d5185445 msr erxstatus_el1, x5
+ [0-9a-f]+: d5385445 mrs x5, erxstatus_el1
+ [0-9a-f]+: d5185465 msr erxaddr_el1, x5
+ [0-9a-f]+: d5385465 mrs x5, erxaddr_el1
+ [0-9a-f]+: d5185505 msr erxmisc0_el1, x5
+ [0-9a-f]+: d5385505 mrs x5, erxmisc0_el1
+ [0-9a-f]+: d5185525 msr erxmisc1_el1, x5
+ [0-9a-f]+: d5385525 mrs x5, erxmisc1_el1
+ [0-9a-f]+: d53c5265 mrs x5, vsesr_el2
+ [0-9a-f]+: d518c125 msr disr_el1, x5
+ [0-9a-f]+: d538c125 mrs x5, disr_el1
+ [0-9a-f]+: d53cc125 mrs x5, vdisr_el2
diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s
index f519682..2a6b06c 100644
--- a/gas/testsuite/gas/aarch64/sysreg-2.s
+++ b/gas/testsuite/gas/aarch64/sysreg-2.s
@@ -13,3 +13,20 @@
rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x7 r=1 w=0
+
+ /* RAS extension. */
+
+ rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
+ rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
+
+ rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
+ rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
+ rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
+ rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
+
+ rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
+ rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
+
+ rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
+ rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
+ rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 84ef3c8..5a7c7d1 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,13 @@
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+ * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
+ "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
+ "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
+ (aarch64_sys_reg_supported_p): Add architecture feature tests for
+ new registers.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (aarch64_feature_ras): New.
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 9522ce2..68fbede 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2862,7 +2862,16 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "esr_el2", CPENC(3,4,C5,C2,0), 0 },
{ "esr_el3", CPENC(3,6,C5,C2,0), 0 },
{ "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
+ { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT }, /* RO */
{ "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
+ { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT }, /* RO */
+ { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
+ { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT }, /* RO */
+ { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
+ { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
+ { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
+ { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
+ { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
{ "far_el1", CPENC(3,0,C6,C0,0), 0 },
{ "far_el2", CPENC(3,4,C6,C0,0), 0 },
{ "far_el3", CPENC(3,6,C6,C0,0), 0 },
@@ -2888,6 +2897,8 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
{ "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
{ "isr_el1", CPENC(3,0,C12,C1,0), 0 }, /* RO */
+ { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
+ { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
{ "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
{ "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
{ "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
@@ -3154,6 +3165,32 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
+ /* RAS extension. */
+
+ /* ERRIDR_EL1 and ERRSELR_EL1. */
+ if ((reg->value == CPENC (3, 0, C5, C3, 0)
+ || reg->value == CPENC (3, 0, C5, C3, 1))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
+ return FALSE;
+
+ /* ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1, ERXMISC0_EL1 AND
+ ERXMISC1_EL1. */
+ if ((reg->value == CPENC (3, 0, C5, C3, 0)
+ || reg->value == CPENC (3, 0, C5, C3 ,1)
+ || reg->value == CPENC (3, 0, C5, C3, 2)
+ || reg->value == CPENC (3, 0, C5, C3, 3)
+ || reg->value == CPENC (3, 0, C5, C5, 0)
+ || reg->value == CPENC (3, 0, C5, C5, 1))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
+ return FALSE;
+
+ /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
+ if ((reg->value == CPENC (3, 4, C5, C2, 3)
+ || reg->value == CPENC (3, 0, C12, C1, 1)
+ || reg->value == CPENC (3, 4, C12, C1, 1))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
+ return FALSE;
+
return TRUE;
}