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[binutils-gdb] [ARM] Support for ARMv8.1 Adv.SIMD extension
- From: Jiong Wang <jiwang at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 2 Jun 2015 11:37:56 -0000
- Subject: [binutils-gdb] [ARM] Support for ARMv8.1 Adv.SIMD extension
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=d6b4b13ed2859a1eafd6c94c0dc64b20fdbde1ba
commit d6b4b13ed2859a1eafd6c94c0dc64b20fdbde1ba
Author: Matthew Wahab <matthew.wahab@arm.com>
Date: Tue Jun 2 12:35:21 2015 +0100
[ARM] Support for ARMv8.1 Adv.SIMD extension
Diff:
---
gas/config/tc-arm.c | 13 +++++++++++++
gas/doc/c-arm.texi | 7 +++++--
include/opcode/arm.h | 6 ++++++
opcodes/arm-dis.c | 19 +++++++++++++++++++
4 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index ece5ebc..c69a942 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -259,6 +259,8 @@ static const arm_feature_set fpu_crypto_ext_armv8 =
ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
static const arm_feature_set crc_ext_armv8 =
ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
+static const arm_feature_set fpu_neon_ext_v8_1 =
+ ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA);
static int mfloat_abi_opt = -1;
/* Record user cpu selection for object attributes. */
@@ -12916,6 +12918,8 @@ struct neon_tab_entry
X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
+ X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
+ X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
X(vshl, 0x0000400, N_INV, 0x0800510), \
X(vqshl, 0x0000410, N_INV, 0x0800710), \
X(vand, 0x0000110, N_INV, 0x0800030), \
@@ -19815,6 +19819,11 @@ static const struct asm_opcode insns[] =
NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
+ /* ARM v8.1 extension. */
+ nUF(vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
+ nUF(vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
+ nUF(vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
+ nUF(vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
/* Two address, int/float. Types S8 S16 S32 F32. */
NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
@@ -24698,6 +24707,9 @@ static const struct arm_option_extension_value_table arm_extensions[] =
| ARM_EXT_DIV),
ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
+ ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8,
+ ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
+ ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ANY),
{ NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE }
@@ -24755,6 +24767,7 @@ static const struct arm_option_fpu_value_table arm_fpus[] =
{"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
{"crypto-neon-fp-armv8",
FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
+ {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
{NULL, ARM_ARCH_NONE}
};
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 85ff20d..afbd9f9 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -179,7 +179,9 @@ architectures),
@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
@code{virt} (Virtualization Extensions for v7-A architecture, implies
@code{idiv}),
-@code{pan} (Priviliged Access Never Extensions for v8-A architecture)
+@code{pan} (Priviliged Access Never Extensions for v8-A architecture),
+@code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
+@code{simd})
and
@code{xscale}.
@@ -271,8 +273,9 @@ The following format options are recognized:
@code{neon},
@code{neon-vfpv4},
@code{neon-fp-armv8},
-and
@code{crypto-neon-fp-armv8}.
+and
+@code{neon-fp-armv8-1},
In addition to determining which instructions are assembled, this option
also affects the way in which the @code{.double} assembler directive behaves
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 9736943..d88ff27 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -85,6 +85,7 @@
#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */
#define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */
#define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */
+#define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */
/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
@@ -203,6 +204,11 @@
#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
#define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
+#define FPU_ARCH_NEON_VFP_ARMV8_1 \
+ ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
+ | FPU_VFP_ARMV8 \
+ | FPU_NEON_EXT_RDMA)
+
#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 3e1315f..e9f4425 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1194,6 +1194,12 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000a10, 0xfe800f10,
"vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3000b10, 0xff800f10,
+ "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3000c10, 0xff800f10,
+ "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
/* One register and an immediate value. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -1447,6 +1453,19 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800a40, 0xfe800f50,
"vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf2800e40, 0xff800f50,
+ "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf2800f40, 0xff800f50,
+ "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3800e40, 0xff800f50,
+ "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3800f40, 0xff800f50,
+ "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
+ },
/* Element and structure load/store. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),