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[binutils-gdb] [AArch64] BFD_RELOC_AARCH64_TLSLE_ADD_LO12 should enable overflow check
- From: Jiong Wang <jiwang at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 1 Jun 2015 09:32:36 -0000
- Subject: [binutils-gdb] [AArch64] BFD_RELOC_AARCH64_TLSLE_ADD_LO12 should enable overflow check
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=36e6c1400b94b9da7ba0dff5b3900a8d3e3b0c75
commit 36e6c1400b94b9da7ba0dff5b3900a8d3e3b0c75
Author: Jiong Wang <jiong.wang@arm.com>
Date: Mon Jun 1 10:31:38 2015 +0100
[AArch64] BFD_RELOC_AARCH64_TLSLE_ADD_LO12 should enable overflow check
BFD_RELOC_AARCH64_TLSLE_ADD_LO12 is used to generate simplest
one-instruction addressing for TLS LE model when tls size is smaller
4K. Linker need to make sure there is no TLS offset overflow.
2015-06-01 Jiong Wang <jiong.wang@arm.com>
bfd/
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Set overflow type to
complain_overflow_unsigned for BFD_RELOC_AARCH64_TLSLE_ADD_LO12.
* elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Don't use
PGOFF for BFD_RELOC_AARCH64_TLSLE_ADD_LO12, that will mask off all
potential high overflowed bits.
ld/testsuite/
* ld-aarch64/tprel_add_lo12_overflow.s: New testcase.
* ld-aarch64/tprel_add_lo12_overflow.d: Nex expectation file.
* ld-aarch64/aarch64-elf.exp: Run new testcase.
Diff:
---
bfd/ChangeLog | 7 +++++++
bfd/elfnn-aarch64.c | 2 +-
bfd/elfxx-aarch64.c | 5 ++++-
ld/testsuite/ChangeLog | 6 ++++++
ld/testsuite/ld-aarch64/aarch64-elf.exp | 1 +
ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.d | 6 ++++++
ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.s | 23 +++++++++++++++++++++++
7 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 5ae71b2..678f0cc 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,5 +1,12 @@
2015-06-01 Jiong Wang <jiong.wang@arm.com>
+ * elfnn-aarch64.c (elfNN_aarch64_howto_table): Set overflow type to
+ complain_overflow_unsigned for BFD_RELOC_AARCH64_TLSLE_ADD_LO12.
+ * elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Don't use
+ PGOFF for BFD_RELOC_AARCH64_TLSLE_ADD_LO12.
+
+2015-06-01 Jiong Wang <jiong.wang@arm.com>
+
* elfnn-aarch64.c (aarch64_reloc_got_type): Support
BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15.
(elfNN_aarch64_final_link_relocate): Ditto.
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index bcb25fd..26f20c5 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -1083,7 +1083,7 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
12, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
- complain_overflow_dont, /* complain_on_overflow */
+ complain_overflow_unsigned, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (TLSLE_ADD_TPREL_LO12), /* name */
FALSE, /* partial_inplace */
diff --git a/bfd/elfxx-aarch64.c b/bfd/elfxx-aarch64.c
index 889b0d0..ec0744b 100644
--- a/bfd/elfxx-aarch64.c
+++ b/bfd/elfxx-aarch64.c
@@ -435,11 +435,14 @@ _bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type,
case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
- case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
value = PG_OFFSET (value + addend);
break;
+ case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
+ value = value + addend;
+ break;
+
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
value = (value + addend) & (bfd_vma) 0xffff0000;
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 9857040..b03786c 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,5 +1,11 @@
2015-06-01 Jiong Wang <jiong.wang@arm.com>
+ * ld-aarch64/tprel_add_lo12_overflow.s: New testcase.
+ * ld-aarch64/tprel_add_lo12_overflow.d: Nex expectation file.
+ * ld-aarch64/aarch64-elf.exp: Run new testcase.
+
+2015-06-01 Jiong Wang <jiong.wang@arm.com>
+
* ld-aarch64/emit-relocs-313.s: New test file.
* ld-aarch64/emit-relocs-313.d: Ditto.
* ld-aarch64/aarch64-elf.exp: Run new test.
diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp
index 79b5a3e..09f2a0e 100644
--- a/ld/testsuite/ld-aarch64/aarch64-elf.exp
+++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp
@@ -146,6 +146,7 @@ run_dump_test "gc-relocs-257-dyn"
run_dump_test "gc-relocs-257"
run_dump_test "pr17415"
run_dump_test "tprel_g2_overflow"
+run_dump_test "tprel_add_lo12_overflow"
# ifunc tests
run_dump_test "ifunc-1"
diff --git a/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.d b/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.d
new file mode 100644
index 0000000..297ee22
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.d
@@ -0,0 +1,6 @@
+#name: TLS offset out of range - TPREL_ADD_LO12
+#source: tprel_add_lo12_overflow.s
+#as:
+#ld: -e0
+#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_TLSLE_ADD_TPREL_LO12 against symbol `i' .*
+
diff --git a/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.s b/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.s
new file mode 100644
index 0000000..7c93d0d
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.s
@@ -0,0 +1,23 @@
+ .cpu generic
+ .global ff
+ .section .tdata,"awT",%progbits
+ .align 2
+ .type ff, %object
+ # Maximum 12bit - 16byte TCB header is the upper limit
+ # for tprel_add_lo12
+ .size ff, 4096 - 16
+ff:
+ .zero 4096 - 16
+ .global i
+ .type i, %object
+ .size i, 4
+i:
+ .zero 4
+ .text
+ .align 2
+ .global main
+ .type main, %function
+main:
+ add x0, x0, #:tprel_lo12:i
+ ret
+ .size main, .-main