This is the mail archive of the
binutils-cvs@sourceware.org
mailing list for the binutils project.
src bfd/ChangeLog bfd/cpu-ia64-opc.c gas/Chang ...
- From: gingold at sourceware dot org
- To: binutils-cvs at sourceware dot org
- Date: 4 Sep 2012 13:57:46 -0000
- Subject: src bfd/ChangeLog bfd/cpu-ia64-opc.c gas/Chang ...
CVSROOT: /cvs/src
Module name: src
Branch: binutils-2_23-branch
Changes by: gingold@sourceware.org 2012-09-04 13:57:46
Modified files:
bfd : ChangeLog cpu-ia64-opc.c
gas : ChangeLog
gas/config : tc-ia64.c
gas/testsuite : ChangeLog
gas/testsuite/gas/ia64: ia64.exp opc-i.d opc-m.d
include/opcode : ChangeLog ia64.h
opcodes : ChangeLog ia64-asmtab.c ia64-asmtab.h
ia64-gen.c ia64-ic.tbl ia64-opc-i.c
ia64-opc-m.c ia64-opc.h ia64-raw.tbl
ia64-waw.tbl
Log message:
bfd/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* cpu-ia64-opc.c (ins_cnt6a): New function.
(ext_cnt6a): Ditto.
(ins_strd5b): Ditto.
(ext_strd5b): Ditto.
(elf64_ia64_operands): Add new operand types.
gas/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* config/tc-ia64.c (reg_symbol): Add a new register.
(indirect_reg): Ditto.
(pseudo_func): Add new symbolic constants.
(operand_match): Add new operand types recognition.
(operand_insn): Add new register recognition.
(md_begin): Add new register definition.
(specify_resource): Add new register recognition.
gas/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* gas/testsuite/gas/ia64/psn.d: New file.
* gas/testsuite/gas/ia64/psn.s: New file.
* gas/testsuite/gas/ia64/ia64.exp: Add new testcase.
* gas/testsuite/gas/ia64/opc-i.d: Fixed failing tests.
* gas/testsuite/gas/ia64/opc-m.d: Ditto.
include/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64.h (ia64_opnd): Add new operand types.
opcodes/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64-asmtab.h (completer_index): Extend bitfield to full uint.
* ia64-gen.c: Promote completer index type to longlong.
(irf_operand): Add new register recognition.
(in_iclass_mov_x): Add an entry for the new mov_* instruction type.
(lookup_specifier): Add new resource recognition.
(insert_bit_table_ent): Relax abort condition according to the
changed completer index type.
(print_dis_table): Fix printf format for completer index.
* ia64-ic.tbl: Add a new instruction class.
* ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
* ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
* ia64-opc.h: Define short names for new operand types.
* ia64-raw.tbl: Add new RAW resource for DAHR register.
* ia64-waw.tbl: Add new WAW resource for DAHR register.
* ia64-asmtab.c: Regenerate.
Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/bfd/ChangeLog.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.5758.2.9&r2=1.5758.2.10
http://sourceware.org/cgi-bin/cvsweb.cgi/src/bfd/cpu-ia64-opc.c.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.17&r2=1.17.22.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/ChangeLog.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.4769.2.4&r2=1.4769.2.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/config/tc-ia64.c.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.219&r2=1.219.2.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.2057.2.4&r2=1.2057.2.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/ia64/ia64.exp.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.44&r2=1.44.6.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/ia64/opc-i.d.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.9&r2=1.9.24.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/ia64/opc-m.d.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.7&r2=1.7.24.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/include/opcode/ChangeLog.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.466.4.1&r2=1.466.4.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/include/opcode/ia64.h.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.13&r2=1.13.16.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.1831.2.8&r2=1.1831.2.9
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ia64-asmtab.c.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.30&r2=1.30.38.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ia64-asmtab.h.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.6&r2=1.6.22.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ia64-gen.c.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.30&r2=1.30.4.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ia64-ic.tbl.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.12&r2=1.12.38.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ia64-opc-i.c.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.10&r2=1.10.22.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ia64-opc-m.c.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.11&r2=1.11.22.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ia64-opc.h.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.8&r2=1.8.52.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ia64-raw.tbl.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.6&r2=1.6.38.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ia64-waw.tbl.diff?cvsroot=src&only_with_tag=binutils-2_23-branch&r1=1.6&r2=1.6.38.1