XSTORMY16 Instruction Documentation

Instructions

Instructions for each machine:

xstormy16 - Xstormy16 CPU core

MEM - Memory
ALU - ALU
BR - Branch
alphabetically

Individual instructions descriptions

adcgrgr - ADD carry and general register to general register

machines: base

syntax: adc $Rd,$Rs

format:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f-op1 f-op2 f-Rs f-Rd

0x4 0xb Rs Rd

semantics: (sequence ((HI value) (HI newpsw)) (set value (addc Rd Rs psw-cy)) (set newpsw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (add-oflag HI Rd Rs psw-cy) 4) (sll HI (add-cflag HI Rd Rs psw-cy) 2)) (or (and (srl HI (addc HI (and Rd 15) (and Rs 15) psw-cy) 1) 8) (sll (index-of Rd) 12))))) (set (reg HI h-gr (index-of Rd)) value) (set psw newpsw)) </plaintext></font> </li> </ul> <a name="insn-adcgrimm16"></a> <h3>adcgrimm16 - ADD carry and 16-bit immediate to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>adc $Rd,#$imm16</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> <td> 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> <td> f-imm16 </td> </tr> <tr> <td> 0x3 </td> <td> 0x1 </td> <td> 0x5 </td> <td> Rd </td> <td> imm16 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI value) (HI newpsw)) (set value (addc Rd imm16 psw-cy)) (set newpsw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (add-oflag HI Rd imm16 psw-cy) 4) (sll HI (add-cflag HI Rd imm16 psw-cy) 2)) (or (and (srl HI (addc HI (and Rd 15) (and imm16 15) psw-cy) 1) 8) (sll (index-of Rd) 12))))) (set (reg HI h-gr (index-of Rd)) value) (set psw newpsw)) </plaintext></font> </li> </ul> <a name="insn-adcgrimm4"></a> <h3>adcgrimm4 - ADD carry and 4-bit immediate to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>adc $Rd,#$imm4</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-imm4 </td> <td> f-Rd </td> </tr> <tr> <td> 0x5 </td> <td> 0x3 </td> <td> imm4 </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI value) (HI newpsw)) (set value (addc Rd imm4 psw-cy)) (set newpsw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (add-oflag HI Rd imm4 psw-cy) 4) (sll HI (add-cflag HI Rd imm4 psw-cy) 2)) (or (and (srl HI (addc HI (and Rd 15) (and imm4 15) psw-cy) 1) 8) (sll (index-of Rd) 12))))) (set (reg HI h-gr (index-of Rd)) value) (set psw newpsw)) </plaintext></font> </li> </ul> <a name="insn-adcimm8"></a> <h3>adcimm8 - ADD carry and 8-bit immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>adc Rx,#$imm8</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-imm8 </td> </tr> <tr> <td> 0x5 </td> <td> 0xb </td> <td> imm8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI value) (HI newpsw)) (set value (addc (reg HI h-gr Rpsw) imm8 psw-cy)) (set newpsw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (add-oflag HI (reg HI h-gr Rpsw) imm8 psw-cy) 4) (sll HI (add-cflag HI (reg HI h-gr Rpsw) imm8 psw-cy) 2)) (or (and (srl HI (addc HI (and (reg HI h-gr Rpsw) 15) (and imm8 15) psw-cy) 1) 8) (sll Rpsw 12))))) (set (reg HI h-gr Rpsw) value) (set psw newpsw)) </plaintext></font> </li> </ul> <a name="insn-addgrgr"></a> <h3>addgrgr - ADD general register to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>add $Rd,$Rs</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-Rs </td> <td> f-Rd </td> </tr> <tr> <td> 0x4 </td> <td> 0x9 </td> <td> Rs </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI value) (HI newpsw)) (set value (addc Rd Rs 0)) (set newpsw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (add-oflag HI Rd Rs 0) 4) (sll HI (add-cflag HI Rd Rs 0) 2)) (or (and (srl HI (addc HI (and Rd 15) (and Rs 15) 0) 1) 8) (sll (index-of Rd) 12))))) (set (reg HI h-gr (index-of Rd)) value) (set psw newpsw)) </plaintext></font> </li> </ul> <a name="insn-addgrimm16"></a> <h3>addgrimm16 - ADD 16-bit immediate to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>add $Rd,#$imm16</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> <td> 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> <td> f-imm16 </td> </tr> <tr> <td> 0x3 </td> <td> 0x1 </td> <td> 0x4 </td> <td> Rd </td> <td> imm16 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI value) (HI newpsw)) (set value (addc Rd imm16 0)) (set newpsw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (add-oflag HI Rd imm16 0) 4) (sll HI (add-cflag HI Rd imm16 0) 2)) (or (and (srl HI (addc HI (and Rd 15) (and imm16 15) 0) 1) 8) (sll (index-of Rd) 12))))) (set (reg HI h-gr (index-of Rd)) value) (set psw newpsw)) </plaintext></font> </li> </ul> <a name="insn-addgrimm4"></a> <h3>addgrimm4 - ADD 4-bit immediate to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>add $Rd,#$imm4</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-imm4 </td> <td> f-Rd </td> </tr> <tr> <td> 0x5 </td> <td> 0x1 </td> <td> imm4 </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI value) (HI newpsw)) (set value (addc Rd imm4 0)) (set newpsw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (add-oflag HI Rd imm4 0) 4) (sll HI (add-cflag HI Rd imm4 0) 2)) (or (and (srl HI (addc HI (and Rd 15) (and imm4 15) 0) 1) 8) (sll (index-of Rd) 12))))) (set (reg HI h-gr (index-of Rd)) value) (set psw newpsw)) </plaintext></font> </li> </ul> <a name="insn-addimm8"></a> <h3>addimm8 - ADD 8-bit immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>add Rx,#$imm8</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-imm8 </td> </tr> <tr> <td> 0x5 </td> <td> 0x9 </td> <td> imm8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI value) (HI newpsw)) (set value (addc (reg HI h-gr Rpsw) imm8 0)) (set newpsw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (add-oflag HI (reg HI h-gr Rpsw) imm8 0) 4) (sll HI (add-cflag HI (reg HI h-gr Rpsw) imm8 0) 2)) (or (and (srl HI (addc HI (and (reg HI h-gr Rpsw) 15) (and imm8 15) 0) 1) 8) (sll Rpsw 12))))) (set (reg HI h-gr Rpsw) value) (set psw newpsw)) </plaintext></font> </li> </ul> <a name="insn-andgrgr"></a> <h3>andgrgr - AND general register with general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>and $Rd,$Rs</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-Rs </td> <td> f-Rd </td> </tr> <tr> <td> 0x4 </td> <td> 0x0 </td> <td> Rs </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (and Rd Rs)) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-andgrimm16"></a> <h3>andgrimm16 - AND general register with 16-bit immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>and $Rd,#$imm16</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> <td> 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> <td> f-imm16 </td> </tr> <tr> <td> 0x3 </td> <td> 0x1 </td> <td> 0x0 </td> <td> Rd </td> <td> imm16 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (and Rd imm16)) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-andimm8"></a> <h3>andimm8 - AND with 8-bit immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>and Rx,#$imm8</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-imm8 </td> </tr> <tr> <td> 0x4 </td> <td> 0x1 </td> <td> imm8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (and (reg HI h-gr Rpsw) imm8)) (set (reg HI h-gr Rpsw) nvalue) (set psw (or (and psw 3996) (or (sll Rpsw 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-asrgrgr"></a> <h3>asrgrgr - Arithmetic shift right general register by general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>asr $Rd,$Rs</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-Rs </td> <td> f-Rd </td> </tr> <tr> <td> 0x3 </td> <td> 0x6 </td> <td> Rs </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue) (HI newpsw)) (set nvalue (sra HI Rd (and Rs 15))) (set newpsw (or (or (and psw 3992) (sll (and (and SI (if SI (eq (and Rs 15) 0) psw-cy (srl Rd (sub (and Rs 15) 1))) 1) 1) 2)) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6)))))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw newpsw)) </plaintext></font> </li> </ul> <a name="insn-asrgrimm"></a> <h3>asrgrimm - Arithmetic shift right general register by immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>asr $Rd,#$imm4</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-imm4 </td> <td> f-Rd </td> </tr> <tr> <td> 0x3 </td> <td> 0x7 </td> <td> imm4 </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue) (HI newpsw)) (set nvalue (sra HI Rd imm4)) (set newpsw (or (or (and psw 3992) (sll (and (and SI (if SI (eq imm4 0) psw-cy (srl Rd (sub imm4 1))) 1) 1) 2)) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6)))))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw newpsw)) </plaintext></font> </li> </ul> <a name="insn-bcc"></a> <h3>bcc - Conditional branch on flag registers</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>b$bcond2 ${rel8-2}</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-rel8-2 </td> </tr> <tr> <td> 0xd </td> <td> bcond2 </td> <td> rel8-2 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((BI tmp)) (case bcond2 ((0) (set tmp (not (xor psw-s psw-ov)))) ((1) (set tmp (not psw-cy))) ((2) (set tmp (xor psw-s psw-ov))) ((3) (set tmp psw-cy)) ((4) (set tmp (not (or (xor psw-s psw-ov) psw-z16)))) ((5) (set tmp (not (or psw-cy psw-z16)))) ((6) (set tmp (or (xor psw-s psw-ov) psw-z16))) ((7) (set tmp (or psw-cy psw-z16))) ((8) (set tmp (not psw-s))) ((9) (set tmp (not psw-ov))) ((10) (set tmp psw-s)) ((11) (set tmp psw-ov)) ((12) (set tmp (not psw-z8))) ((13) (set tmp (not psw-z16))) ((14) (set tmp psw-z8)) ((15) (set tmp psw-z16))) (if tmp (set pc rel8-2))) </plaintext></font> </li> </ul> <a name="insn-bccgrgr"></a> <h3>bccgrgr - Conditional branch comparing general register with general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>b$bcond5 $Rd,$Rs,$rel12</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-Rs </td> <td> f-Rd </td> <td> f-op5 </td> <td> f-rel12 </td> </tr> <tr> <td> 0x0 </td> <td> 0xd </td> <td> Rs </td> <td> Rd </td> <td> bcond5 </td> <td> rel12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (sequence ((HI value)) (set value (sub Rd Rs)) (set psw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (sub-oflag HI Rd Rs 0) 4) (sll HI (sub-cflag HI Rd Rs 0) 2)) (or (and (srl HI (sub HI (and Rd 15) (and Rs 15)) 1) 8) (sll (index-of Rd) 12)))))) (sequence ((BI tmp)) (case bcond5 ((0) (set tmp (not (xor psw-s psw-ov)))) ((1) (set tmp (not psw-cy))) ((2) (set tmp (xor psw-s psw-ov))) ((3) (set tmp psw-cy)) ((4) (set tmp (not (or (xor psw-s psw-ov) psw-z16)))) ((5) (set tmp (not (or psw-cy psw-z16)))) ((6) (set tmp (or (xor psw-s psw-ov) psw-z16))) ((7) (set tmp (or psw-cy psw-z16))) ((8) (set tmp (not psw-s))) ((9) (set tmp (not psw-ov))) ((10) (set tmp psw-s)) ((11) (set tmp psw-ov)) ((12) (set tmp (not psw-z8))) ((13) (set tmp (not psw-z16))) ((14) (set tmp psw-z8)) ((15) (set tmp psw-z16))) (if tmp (set pc rel12)))) </plaintext></font> </li> </ul> <a name="insn-bccgrimm8"></a> <h3>bccgrimm8 - Conditional branch comparing general register with 8-bit immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>b$bcond5 $Rm,#$imm8,$rel12</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 12 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-Rm </td> <td> f-op2m </td> <td> f-imm8 </td> <td> f-op5 </td> <td> f-rel12 </td> </tr> <tr> <td> 0x2 </td> <td> Rm </td> <td> 0x0 </td> <td> imm8 </td> <td> bcond5 </td> <td> rel12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (sequence ((HI value)) (set value (sub Rm imm8)) (set psw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (sub-oflag HI Rm imm8 0) 4) (sll HI (sub-cflag HI Rm imm8 0) 2)) (or (and (srl HI (sub HI (and Rm 15) (and imm8 15)) 1) 8) (sll (index-of Rm) 12)))))) (sequence ((BI tmp)) (case bcond5 ((0) (set tmp (not (xor psw-s psw-ov)))) ((1) (set tmp (not psw-cy))) ((2) (set tmp (xor psw-s psw-ov))) ((3) (set tmp psw-cy)) ((4) (set tmp (not (or (xor psw-s psw-ov) psw-z16)))) ((5) (set tmp (not (or psw-cy psw-z16)))) ((6) (set tmp (or (xor psw-s psw-ov) psw-z16))) ((7) (set tmp (or psw-cy psw-z16))) ((8) (set tmp (not psw-s))) ((9) (set tmp (not psw-ov))) ((10) (set tmp psw-s)) ((11) (set tmp psw-ov)) ((12) (set tmp (not psw-z8))) ((13) (set tmp (not psw-z16))) ((14) (set tmp psw-z8)) ((15) (set tmp psw-z16))) (if tmp (set pc rel12)))) </plaintext></font> </li> </ul> <a name="insn-bccimm16"></a> <h3>bccimm16 - Conditional branch comparing general register with 16-bit immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>b$bcond2 Rx,#$imm16,${rel8-4}</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 </td> <td> 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-rel8-4 </td> <td> f-imm16 </td> </tr> <tr> <td> 0xc </td> <td> bcond2 </td> <td> rel8-4 </td> <td> imm16 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (sequence ((HI value)) (set value (sub (reg HI h-gr Rpsw) imm16)) (set psw (or (or (and psw 3968) (or (or (eq (and value 255) 0) (sll HI (eq HI value 0) 1)) (or (sll HI (c-call BI "parity" value) 5) (sll HI (lt QI (srl value (mul 1 8)) 0) 6)))) (or (or (sll HI (sub-oflag HI (reg HI h-gr Rpsw) imm16 0) 4) (sll HI (sub-cflag HI (reg HI h-gr Rpsw) imm16 0) 2)) (or (and (srl HI (sub HI (and (reg HI h-gr Rpsw) 15) (and imm16 15)) 1) 8) (sll Rpsw 12)))))) (sequence ((BI tmp)) (case bcond2 ((0) (set tmp (not (xor psw-s psw-ov)))) ((1) (set tmp (not psw-cy))) ((2) (set tmp (xor psw-s psw-ov))) ((3) (set tmp psw-cy)) ((4) (set tmp (not (or (xor psw-s psw-ov) psw-z16)))) ((5) (set tmp (not (or psw-cy psw-z16)))) ((6) (set tmp (or (xor psw-s psw-ov) psw-z16))) ((7) (set tmp (or psw-cy psw-z16))) ((8) (set tmp (not psw-s))) ((9) (set tmp (not psw-ov))) ((10) (set tmp psw-s)) ((11) (set tmp psw-ov)) ((12) (set tmp (not psw-z8))) ((13) (set tmp (not psw-z16))) ((14) (set tmp psw-z8)) ((15) (set tmp psw-z16))) (if tmp (set pc rel8-4)))) </plaintext></font> </li> </ul> <a name="insn-bgr"></a> <h3>bgr - Branch to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>br $Rd</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> </tr> <tr> <td> 0x0 </td> <td> 0x0 </td> <td> 0x2 </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(set pc (add (add pc 2) Rd)) </plaintext></font> </li> </ul> <a name="insn-bngrgr"></a> <h3>bngrgr - Test bit in general register by general register and branch if 0</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>bn $Rd,$Rs,$rel12</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-Rs </td> <td> f-Rd </td> <td> f-op5 </td> <td> f-rel12 </td> </tr> <tr> <td> 0x0 </td> <td> 0x6 </td> <td> Rs </td> <td> Rd </td> <td> 0x0 </td> <td> rel12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rpsw (index-of Rd)) (if (eq (and Rd (sll 1 Rs)) 0) (set pc rel12))) </plaintext></font> </li> </ul> <a name="insn-bngrimm4"></a> <h3>bngrimm4 - Test bit in general register by immediate and branch if 0</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>bn $Rd,#$imm4,$rel12</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-imm4 </td> <td> f-Rd </td> <td> f-op5 </td> <td> f-rel12 </td> </tr> <tr> <td> 0x0 </td> <td> 0x4 </td> <td> imm4 </td> <td> Rd </td> <td> 0x0 </td> <td> rel12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rpsw (index-of Rd)) (if (eq (and Rd (sll 1 imm4)) 0) (set pc rel12))) </plaintext></font> </li> </ul> <a name="insn-bnhmemimm"></a> <h3>bnhmemimm - Test bit in memory by immediate and branch if 0</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>bn $hmem8,#$imm3b,$rel12</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 </td> <td> 16 </td> <td> 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-hmem8 </td> <td> f-op5a </td> <td> f-imm3b </td> <td> f-rel12 </td> </tr> <tr> <td> 0x7 </td> <td> 0xe </td> <td> hmem8 </td> <td> 0x0 </td> <td> imm3b </td> <td> rel12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if (eq (and (mem QI hmem8) (sll 1 imm3b)) 0) (set pc rel12)) </plaintext></font> </li> </ul> <a name="insn-bnlmemimm"></a> <h3>bnlmemimm - Test bit in memory by immediate and branch if 0</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>bn $lmem8,#$imm3b,$rel12</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 </td> <td> 16 </td> <td> 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-lmem8 </td> <td> f-op5a </td> <td> f-imm3b </td> <td> f-rel12 </td> </tr> <tr> <td> 0x7 </td> <td> 0xc </td> <td> lmem8 </td> <td> 0x0 </td> <td> imm3b </td> <td> rel12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if (eq (and (mem QI lmem8) (sll 1 imm3b)) 0) (set pc rel12)) </plaintext></font> </li> </ul> <a name="insn-bpgrgr"></a> <h3>bpgrgr - Test bit in general register by general register and branch if 1</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>bp $Rd,$Rs,$rel12</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-Rs </td> <td> f-Rd </td> <td> f-op5 </td> <td> f-rel12 </td> </tr> <tr> <td> 0x0 </td> <td> 0x7 </td> <td> Rs </td> <td> Rd </td> <td> 0x0 </td> <td> rel12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rpsw (index-of Rd)) (if (ne (and Rd (sll 1 Rs)) 0) (set pc rel12))) </plaintext></font> </li> </ul> <a name="insn-bpgrimm4"></a> <h3>bpgrimm4 - Test bit in general register by immediate and branch if 1</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>bp $Rd,#$imm4,$rel12</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-imm4 </td> <td> f-Rd </td> <td> f-op5 </td> <td> f-rel12 </td> </tr> <tr> <td> 0x0 </td> <td> 0x5 </td> <td> imm4 </td> <td> Rd </td> <td> 0x0 </td> <td> rel12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rpsw (index-of Rd)) (if (ne (and Rd (sll 1 imm4)) 0) (set pc rel12))) </plaintext></font> </li> </ul> <a name="insn-bphmemimm"></a> <h3>bphmemimm - Test bit in memory by immediate and branch if 1</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>bp $hmem8,#$imm3b,$rel12</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 </td> <td> 16 </td> <td> 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-hmem8 </td> <td> f-op5a </td> <td> f-imm3b </td> <td> f-rel12 </td> </tr> <tr> <td> 0x7 </td> <td> 0xf </td> <td> hmem8 </td> <td> 0x0 </td> <td> imm3b </td> <td> rel12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if (ne (and (mem QI hmem8) (sll 1 imm3b)) 0) (set pc rel12)) </plaintext></font> </li> </ul> <a name="insn-bplmemimm"></a> <h3>bplmemimm - Test bit in memory by immediate and branch if 1</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>bp $lmem8,#$imm3b,$rel12</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 </td> <td> 16 </td> <td> 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-lmem8 </td> <td> f-op5a </td> <td> f-imm3b </td> <td> f-rel12 </td> </tr> <tr> <td> 0x7 </td> <td> 0xd </td> <td> lmem8 </td> <td> 0x0 </td> <td> imm3b </td> <td> rel12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if (ne (and (mem QI lmem8) (sll 1 imm3b)) 0) (set pc rel12)) </plaintext></font> </li> </ul> <a name="insn-br"></a> <h3>br - Branch</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>br $rel12a</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 8 9 10 11 12 13 14 </td> <td> 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-rel12a </td> <td> f-op4b </td> </tr> <tr> <td> 0x1 </td> <td> rel12a </td> <td> 0x0 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(set pc rel12a) </plaintext></font> </li> </ul> <a name="insn-brk"></a> <h3>brk - brk</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>brk</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op </td> </tr> <tr> <td> 0x5 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(c-call VOID "do_brk") </plaintext></font> </li> </ul> <a name="insn-callfimm"></a> <h3>callfimm - Call far to absolute address</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>callf $abs24</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-abs24 </td> </tr> <tr> <td> 0x0 </td> <td> 0x1 </td> <td> abs24 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set (mem SI sp) (add pc 4)) (set sp (add sp 4)) (set pc abs24)) </plaintext></font> </li> </ul> <a name="insn-callgr"></a> <h3>callgr - Call to general registers</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>call $Rbj,$Rd</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 </td> <td> 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3b </td> <td> f-Rbj </td> <td> f-Rd </td> </tr> <tr> <td> 0x0 </td> <td> 0x0 </td> <td> 0x5 </td> <td> Rbj </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set (mem SI sp) (add pc 2)) (set sp (add sp 4)) (set pc (join SI HI Rbj Rd))) </plaintext></font> </li> </ul> <a name="insn-callrgr"></a> <h3>callrgr - Call relative to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>callr $Rd</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> </tr> <tr> <td> 0x0 </td> <td> 0x0 </td> <td> 0x1 </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set (mem SI sp) (add pc 2)) (set sp (add sp 4)) (set pc (add Rd (add pc 2)))) </plaintext></font> </li> </ul> <a name="insn-callrimm"></a> <h3>callrimm - Call relative to immediate address</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>callr $rel12a</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 8 9 10 11 12 13 14 </td> <td> 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-rel12a </td> <td> f-op4b </td> </tr> <tr> <td> 0x1 </td> <td> rel12a </td> <td> 0x1 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set (mem SI sp) (add pc 2)) (set sp (add sp 4)) (set pc rel12a)) </plaintext></font> </li> </ul> <a name="insn-cbwgr"></a> <h3>cbwgr - Sign-extend byte in general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>cbw $Rd</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> </tr> <tr> <td> 0x3 </td> <td> 0x0 </td> <td> 0xa </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (ext HI (trunc QI Rd))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-clr1grgr"></a> <h3>clr1grgr - Clear bit in general register by general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>clr1 $Rd,$Rs</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-Rs </td> <td> f-Rd </td> </tr> <tr> <td> 0x0 </td> <td> 0xa </td> <td> Rs </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (and Rd (inv (sll 1 (and Rs 15))))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-clr1grimm"></a> <h3>clr1grimm - Clear bit in general register by immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>clr1 $Rd,#$imm4</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-imm4 </td> <td> f-Rd </td> </tr> <tr> <td> 0x0 </td> <td> 0x8 </td> <td> imm4 </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (and Rd (inv (sll 1 imm4)))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-clr1hmemimm"></a> <h3>clr1hmemimm - Clear bit in high memory</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>clr1 $hmem8,#$imm3</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-imm3 </td> <td> f-op2m </td> <td> f-hmem8 </td> </tr> <tr> <td> 0xf </td> <td> imm3 </td> <td> 0x0 </td> <td> hmem8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (and (mem QI hmem8) (inv (sll 1 imm3)))) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 0 8)) 0) 6))))) (set (mem QI hmem8) nvalue)) </plaintext></font> </li> </ul> <a name="insn-clr1lmemimm"></a> <h3>clr1lmemimm - Clear bit in low memory</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>clr1 $lmem8,#$imm3</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-imm3 </td> <td> f-op2m </td> <td> f-lmem8 </td> </tr> <tr> <td> 0xe </td> <td> imm3 </td> <td> 0x0 </td> <td> lmem8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (and (mem QI lmem8) (inv (sll 1 imm3)))) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 0 8)) 0) 6))))) (set (mem QI lmem8) nvalue)) </plaintext></font> </li> </ul> <a name="insn-decgrimm2"></a> <h3>decgrimm2 - Decrement general register by 2-bit immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>dec $Rd,#$imm2</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 </td> <td> 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3a </td> <td> f-imm2 </td> <td> f-Rd </td> </tr> <tr> <td> 0x3 </td> <td> 0x0 </td> <td> 0x1 </td> <td> imm2 </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (sub Rd (add imm2 1))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-div"></a> <h3>div - Divide</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>div</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op </td> </tr> <tr> <td> 0xc0 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set R1 (umod R0 R2)) (sequence ((HI nvalue)) (set nvalue (udiv R0 R2)) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))) (set R0 nvalue))) </plaintext></font> </li> </ul> <a name="insn-divlh"></a> <h3>divlh - Divide 32/16</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>divlh</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op </td> </tr> <tr> <td> 0xe0 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((SI value)) (set value (add SI (sll SI (and SI R1 65535) 16) (and SI R0 65535))) (set R1 (umod SI value R2)) (sequence ((HI nvalue)) (set nvalue (udiv SI value R2)) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))) (set R0 nvalue))) </plaintext></font> </li> </ul> <a name="insn-halt"></a> <h3>halt - halt</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>halt</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op </td> </tr> <tr> <td> 0x8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(c-call VOID "do_halt") </plaintext></font> </li> </ul> <a name="insn-hold"></a> <h3>hold - hold</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>hold</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op </td> </tr> <tr> <td> 0xa </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(c-call VOID "do_hold") </plaintext></font> </li> </ul> <a name="insn-holdx"></a> <h3>holdx - holdx</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>holdx</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op </td> </tr> <tr> <td> 0xb </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(c-call VOID "do_holdx") </plaintext></font> </li> </ul> <a name="insn-icallfimm"></a> <h3>icallfimm - Call interrupt far to absolute address</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>icallf $abs24</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-abs24 </td> </tr> <tr> <td> 0x0 </td> <td> 0x3 </td> <td> abs24 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set (mem SI sp) (add pc 4)) (set (mem HI (add sp 4)) psw) (set sp (add sp 6)) (set pc abs24)) </plaintext></font> </li> </ul> <a name="insn-icallgr"></a> <h3>icallgr - Call interrupt to general registers</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>icall $Rbj,$Rd</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 </td> <td> 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3b </td> <td> f-Rbj </td> <td> f-Rd </td> </tr> <tr> <td> 0x0 </td> <td> 0x0 </td> <td> 0x3 </td> <td> Rbj </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set (mem SI sp) (add pc 2)) (set (mem HI (add sp 4)) psw) (set sp (add sp 6)) (set pc (join SI HI Rbj Rd))) </plaintext></font> </li> </ul> <a name="insn-icallrgr"></a> <h3>icallrgr - Call interrupt to general registers pc-relative</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>icallr $Rd</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> </tr> <tr> <td> 0x0 </td> <td> 0x0 </td> <td> 0x3 </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set (mem SI sp) (add pc 2)) (set (mem HI (add sp 4)) psw) (set sp (add sp 6)) (set pc (add Rd (add pc 2)))) </plaintext></font> </li> </ul> <a name="insn-incgrimm2"></a> <h3>incgrimm2 - Increment general register by 2-bit immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>inc $Rd,#$imm2</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 </td> <td> 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3a </td> <td> f-imm2 </td> <td> f-Rd </td> </tr> <tr> <td> 0x3 </td> <td> 0x0 </td> <td> 0x0 </td> <td> imm2 </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (add Rd (add imm2 1))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-iret"></a> <h3>iret - Return from interrupt</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>iret</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op </td> </tr> <tr> <td> 0x2 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set sp (sub sp 6)) (set pc (mem SI sp)) (set psw (mem HI (add sp 4)))) </plaintext></font> </li> </ul> <a name="insn-jmp"></a> <h3>jmp - Jump</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>jmp $Rbj,$Rd</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 </td> <td> 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3b </td> <td> f-Rbj </td> <td> f-Rd </td> </tr> <tr> <td> 0x0 </td> <td> 0x0 </td> <td> 0x2 </td> <td> Rbj </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(set pc (join SI HI Rbj Rd)) </plaintext></font> </li> </ul> <a name="insn-jmpf"></a> <h3>jmpf - Jump far</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>jmpf $abs24</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-abs24 </td> </tr> <tr> <td> 0x0 </td> <td> 0x2 </td> <td> abs24 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(set pc abs24) </plaintext></font> </li> </ul> <a name="insn-maskgrgr"></a> <h3>maskgrgr - Mask insert controlled by general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mask $Rd,$Rs</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-Rs </td> <td> f-Rd </td> </tr> <tr> <td> 0x3 </td> <td> 0x3 </td> <td> Rs </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (or HI (and HI Rd (inv HI Rs)) (and (reg HI h-gr Rpsw) Rs))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-maskgrimm16"></a> <h3>maskgrimm16 - Mask insert controlled by immediate value</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mask $Rd,#$imm16</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> <td> 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> <td> f-imm16 </td> </tr> <tr> <td> 0x3 </td> <td> 0x0 </td> <td> 0xe </td> <td> Rd </td> <td> imm16 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (or (and Rd (inv imm16)) (and (reg HI h-gr Rpsw) imm16))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-movfgrgri"></a> <h3>movfgrgri - Move far memory addressed by register to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 $Rdm,($Rs)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x7 </td> <td> 0x2 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and (or (sll SI R8 16) Rs) 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI (or (sll SI R8 16) Rs)))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) </plaintext></font> </li> </ul> <a name="insn-movfgrgrii"></a> <h3>movfgrgrii - Move far memory addressed by indexed register to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 $Rdm,($Rb,$Rs,$imm12)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 </td> <td> 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5a </td> <td> f-Rb </td> <td> f-imm12 </td> </tr> <tr> <td> 0x7 </td> <td> 0x2 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> Rb </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and (add (join SI HI Rb Rs) imm12) 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI (add (join SI HI Rb Rs) imm12)))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) </plaintext></font> </li> </ul> <a name="insn-movfgrgriipostinc"></a> <h3>movfgrgriipostinc - Move far memory addressed by indexed register postincrement to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 $Rdm,($Rb,$Rs++,$imm12)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 </td> <td> 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5a </td> <td> f-Rb </td> <td> f-imm12 </td> </tr> <tr> <td> 0x6 </td> <td> 0x2 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> Rb </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and (add (join SI HI Rb Rs) imm12) 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI (add (join SI HI Rb Rs) imm12)))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) (set Rs (add Rs (add ws2 1)))) </plaintext></font> </li> </ul> <a name="insn-movfgrgriipredec"></a> <h3>movfgrgriipredec - Move far memory addressed by indexed register predecrement to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 $Rdm,($Rb,--$Rs,$imm12)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 </td> <td> 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5a </td> <td> f-Rb </td> <td> f-imm12 </td> </tr> <tr> <td> 0x6 </td> <td> 0x6 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> Rb </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rs (sub Rs (add ws2 1))) (if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and (add (join SI HI Rb Rs) imm12) 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI (add (join SI HI Rb Rs) imm12)))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))))) </plaintext></font> </li> </ul> <a name="insn-movfgrgripostinc"></a> <h3>movfgrgripostinc - Move far memory addressed by postincrement register to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 $Rdm,($Rs++)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x6 </td> <td> 0x2 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and (join SI HI R8 Rs) 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI (join SI HI R8 Rs)))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) (set Rs (add Rs (add ws2 1)))) </plaintext></font> </li> </ul> <a name="insn-movfgrgripredec"></a> <h3>movfgrgripredec - Move far memory addressed by predecrement register to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 $Rdm,(--$Rs)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x6 </td> <td> 0x6 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rs (sub Rs (add ws2 1))) (if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and (join SI HI R8 Rs) 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI (join SI HI R8 Rs)))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))))) </plaintext></font> </li> </ul> <a name="insn-movfgrigr"></a> <h3>movfgrigr - Move far register to memory addressed by register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 ($Rs),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x7 </td> <td> 0x3 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (set (mem HI (and (join SI HI R8 Rs) 65534)) Rdm) (set (mem QI (join SI HI R8 Rs)) Rdm)) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) </plaintext></font> </li> </ul> <a name="insn-movfgriigr"></a> <h3>movfgriigr - Move far register to memory addressed by indexed register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 ($Rb,$Rs,$imm12),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 </td> <td> 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5a </td> <td> f-Rb </td> <td> f-imm12 </td> </tr> <tr> <td> 0x7 </td> <td> 0x3 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> Rb </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (set (mem HI (and (add (join SI HI Rb Rs) imm12) 4294967294)) Rdm) (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm)) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) </plaintext></font> </li> </ul> <a name="insn-movfgriipostincgr"></a> <h3>movfgriipostincgr - Move far register to memory addressed by indexed register postincrement</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 ($Rb,$Rs++,$imm12),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 </td> <td> 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5a </td> <td> f-Rb </td> <td> f-imm12 </td> </tr> <tr> <td> 0x6 </td> <td> 0x3 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> Rb </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (set (mem HI (and (add (join SI HI Rb Rs) imm12) 4294967294)) Rdm) (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm)) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (set Rs (add Rs (add ws2 1)))) </plaintext></font> </li> </ul> <a name="insn-movfgriipredecgr"></a> <h3>movfgriipredecgr - Move far register to memory addressed by indexed register predecrement</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 ($Rb,--$Rs,$imm12),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 </td> <td> 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5a </td> <td> f-Rb </td> <td> f-imm12 </td> </tr> <tr> <td> 0x6 </td> <td> 0x7 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> Rb </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rs (sub Rs 1)) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (if ws2 (set (mem HI (and (add (join SI HI Rb Rs) imm12) 4294967294)) Rdm) (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm))) </plaintext></font> </li> </ul> <a name="insn-movfgripostincgr"></a> <h3>movfgripostincgr - Move far register to memory addressed by postincrement register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 ($Rs++),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x6 </td> <td> 0x3 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (set (mem HI (and (join SI HI R8 Rs) 65534)) Rdm) (set (mem QI (join SI HI R8 Rs)) Rdm)) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (set Rs (add Rs (add ws2 1)))) </plaintext></font> </li> </ul> <a name="insn-movfgripredecgr"></a> <h3>movfgripredecgr - Move far register to memory addressed by predecrement register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>movf$ws2 (--$Rs),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x6 </td> <td> 0x7 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (set Rs (sub Rs (add ws2 1))) (if ws2 (set (mem HI (and (join SI HI R8 Rs) 65534)) Rdm) (set (mem QI (join SI HI R8 Rs)) Rdm))) </plaintext></font> </li> </ul> <a name="insn-movgrgr"></a> <h3>movgrgr - Move general register to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov $Rd,$Rs</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-Rs </td> <td> f-Rd </td> </tr> <tr> <td> 0x4 </td> <td> 0x6 </td> <td> Rs </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue Rs) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-movgrgri"></a> <h3>movgrgri - Move memory addressed by register to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $Rdm,($Rs)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x7 </td> <td> 0x0 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and Rs 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI Rs))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) </plaintext></font> </li> </ul> <a name="insn-movgrgrii"></a> <h3>movgrgrii - Move memory addressed by indexed register to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $Rdm,($Rs,$imm12)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5 </td> <td> f-imm12 </td> </tr> <tr> <td> 0x7 </td> <td> 0x0 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and (add Rs imm12) 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI (add Rs imm12)))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) </plaintext></font> </li> </ul> <a name="insn-movgrgriipostinc"></a> <h3>movgrgriipostinc - Move memory addressed by indexed register postincrement to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $Rdm,($Rs++,$imm12)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5 </td> <td> f-imm12 </td> </tr> <tr> <td> 0x6 </td> <td> 0x0 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and (add Rs imm12) 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI (add Rs imm12)))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) (set Rs (add Rs (add ws2 1)))) </plaintext></font> </li> </ul> <a name="insn-movgrgriipredec"></a> <h3>movgrgriipredec - Move memory addressed by indexed register predecrement to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $Rdm,(--$Rs,$imm12)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5 </td> <td> f-imm12 </td> </tr> <tr> <td> 0x6 </td> <td> 0x4 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rs (sub Rs (add ws2 1))) (if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and (add Rs imm12) 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI (add Rs imm12)))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))))) </plaintext></font> </li> </ul> <a name="insn-movgrgripostinc"></a> <h3>movgrgripostinc - Move memory addressed by postincrement register to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $Rdm,($Rs++)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x6 </td> <td> 0x0 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and Rs 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI Rs))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) (set Rs (add Rs (add 1 ws2)))) </plaintext></font> </li> </ul> <a name="insn-movgrgripredec"></a> <h3>movgrgripredec - Move memory addressed by predecrement register to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $Rdm,(--$Rs)</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x6 </td> <td> 0x4 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rs (sub Rs (add 1 ws2))) (if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and Rs 65534))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (and 255 (mem QI Rs))) (set (reg HI h-gr (index-of Rdm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))))) </plaintext></font> </li> </ul> <a name="insn-movgrigr"></a> <h3>movgrigr - Move register to memory addressed by register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 ($Rs),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x7 </td> <td> 0x1 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (set (mem HI (and Rs 65534)) Rdm) (set (mem QI Rs) Rdm)) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) </plaintext></font> </li> </ul> <a name="insn-movgriigr"></a> <h3>movgriigr - Move register to memory addressed by indexed register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 ($Rs,$imm12),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5 </td> <td> f-imm12 </td> </tr> <tr> <td> 0x7 </td> <td> 0x1 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (set (mem HI (and (add Rs imm12) 65534)) Rdm) (set (mem QI (add Rs imm12)) Rdm)) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) </plaintext></font> </li> </ul> <a name="insn-movgriipostincgr"></a> <h3>movgriipostincgr - Move register to memory addressed by indexed register postincrement</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 ($Rs++,$imm12),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5 </td> <td> f-imm12 </td> </tr> <tr> <td> 0x6 </td> <td> 0x1 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (set (mem HI (and (add Rs imm12) 65534)) Rdm) (set (mem QI (add Rs imm12)) Rdm)) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (set Rs (add Rs 1))) </plaintext></font> </li> </ul> <a name="insn-movgriipredecgr"></a> <h3>movgriipredecgr - Move register to memory addressed by indexed register predecrement</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 (--$Rs,$imm12),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> <td> 16 17 18 19 </td> <td> 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> <td> f-op5 </td> <td> f-imm12 </td> </tr> <tr> <td> 0x6 </td> <td> 0x5 </td> <td> ws2 </td> <td> Rs </td> <td> 0x1 </td> <td> Rdm </td> <td> 0x0 </td> <td> imm12 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rs (sub Rs 1)) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (if ws2 (set (mem HI (and (add Rs imm12) 65534)) Rdm) (set (mem QI (add Rs imm12)) Rdm))) </plaintext></font> </li> </ul> <a name="insn-movgripostincgr"></a> <h3>movgripostincgr - Move register to memory addressed by postincrement register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 ($Rs++),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x6 </td> <td> 0x1 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (if ws2 (set (mem HI (and Rs 65534)) Rdm) (set (mem QI Rs) Rdm)) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (set Rs (add Rs (add ws2 1)))) </plaintext></font> </li> </ul> <a name="insn-movgripredecgr"></a> <h3>movgripredecgr - Move register to memory addressed by predecrement register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 (--$Rs),$Rdm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 </td> <td> 12 </td> <td> 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-Rs </td> <td> f-op4m </td> <td> f-Rdm </td> </tr> <tr> <td> 0x6 </td> <td> 0x5 </td> <td> ws2 </td> <td> Rs </td> <td> 0x0 </td> <td> Rdm </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence () (set Rs (sub Rs (add ws2 1))) (sequence ((HI nvalue)) (set nvalue Rdm) (set psw (or (and psw 3996) (or (sll (index-of Rdm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (if ws2 (set (mem HI (and Rs 65534)) Rdm) (set (mem QI Rs) Rdm))) </plaintext></font> </li> </ul> <a name="insn-movhgrmem"></a> <h3>movhgrmem - Move high memory to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $Rm,$hmem8</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-Rm </td> <td> f-op2m </td> <td> f-hmem8 </td> </tr> <tr> <td> 0xa </td> <td> Rm </td> <td> ws2 </td> <td> hmem8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and hmem8 65534))) (set (reg HI h-gr (index-of Rm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (mem QI hmem8)) (set (reg HI h-gr (index-of Rm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) </plaintext></font> </li> </ul> <a name="insn-movhighgr"></a> <h3>movhighgr - Move 8 high bits to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov.b $Rd,RxH</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> </tr> <tr> <td> 0x3 </td> <td> 0x0 </td> <td> 0xd </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (or (and Rd 255) (and (reg HI h-gr Rpsw) 65280))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-movhmemgr"></a> <h3>movhmemgr - Move high memory register to byte</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $hmem8,$Rm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-Rm </td> <td> f-op2m </td> <td> f-hmem8 </td> </tr> <tr> <td> 0xb </td> <td> Rm </td> <td> ws2 </td> <td> hmem8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if ws2 (sequence ((HI nvalue)) (set nvalue Rm) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))) (set (mem HI (and lmem8 65534)) nvalue)) (sequence ((HI nvalue)) (set nvalue Rm) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))) (set (mem QI lmem8) nvalue))) </plaintext></font> </li> </ul> <a name="insn-movhmemimm"></a> <h3>movhmemimm - Move immediate to high memory</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $hmem8,#$imm16</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 12 13 14 15 </td> <td> 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-hmem8 </td> <td> f-imm16 </td> </tr> <tr> <td> 0x7 </td> <td> 0x5 </td> <td> ws2 </td> <td> hmem8 </td> <td> imm16 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if ws2 (sequence ((HI nvalue)) (set nvalue imm16) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))) (set (mem HI (and hmem8 65534)) nvalue)) (sequence ((HI nvalue)) (set nvalue (and imm16 255)) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))) (set (mem QI hmem8) nvalue))) </plaintext></font> </li> </ul> <a name="insn-movlgrmem"></a> <h3>movlgrmem - Move low memory to register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $Rm,$lmem8</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-Rm </td> <td> f-op2m </td> <td> f-lmem8 </td> </tr> <tr> <td> 0x8 </td> <td> Rm </td> <td> ws2 </td> <td> lmem8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if ws2 (sequence ((HI nvalue)) (set nvalue (mem HI (and lmem8 65534))) (set (reg HI h-gr (index-of Rm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))))) (sequence ((HI nvalue)) (set nvalue (mem QI lmem8)) (set (reg HI h-gr (index-of Rm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6)))))))) </plaintext></font> </li> </ul> <a name="insn-movlmemgr"></a> <h3>movlmemgr - Move low memory register to byte</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $lmem8,$Rm</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-Rm </td> <td> f-op2m </td> <td> f-lmem8 </td> </tr> <tr> <td> 0x9 </td> <td> Rm </td> <td> ws2 </td> <td> lmem8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if ws2 (sequence ((HI nvalue)) (set nvalue Rm) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))) (set (mem HI (and lmem8 65534)) nvalue)) (sequence ((HI nvalue)) (set nvalue Rm) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))) (set (mem QI lmem8) nvalue))) </plaintext></font> </li> </ul> <a name="insn-movlmemimm"></a> <h3>movlmemimm - Move immediate to low memory</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov$ws2 $lmem8,#$imm16</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 12 13 14 15 </td> <td> 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2a </td> <td> f-op2m </td> <td> f-lmem8 </td> <td> f-imm16 </td> </tr> <tr> <td> 0x7 </td> <td> 0x4 </td> <td> ws2 </td> <td> lmem8 </td> <td> imm16 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(if ws2 (sequence ((HI nvalue)) (set nvalue imm16) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))) (set (mem HI (and lmem8 65534)) nvalue)) (sequence ((HI nvalue)) (set nvalue (and imm16 255)) (set psw (or (and psw 65436) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul ws2 8)) 0) 6))))) (set (mem QI lmem8) nvalue))) </plaintext></font> </li> </ul> <a name="insn-movlowgr"></a> <h3>movlowgr - Move 8 low bits to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov.b $Rd,RxL</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> </tr> <tr> <td> 0x3 </td> <td> 0x0 </td> <td> 0xc </td> <td> Rd </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue (or (and Rd 65280) (and (reg HI h-gr Rpsw) 255))) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 0 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-movwgrimm16"></a> <h3>movwgrimm16 - Move 16-bit immediate to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov.w $Rd,#$imm16</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> <td> 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> <td> f-imm16 </td> </tr> <tr> <td> 0x3 </td> <td> 0x1 </td> <td> 0x3 </td> <td> Rd </td> <td> imm16 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue imm16) (set (reg HI h-gr (index-of Rd)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rd) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-movwgrimm8"></a> <h3>movwgrimm8 - Move 8-bit immediate to general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov.w $Rm,#$imm8small</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 </td> <td> 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-Rm </td> <td> f-op2m </td> <td> f-imm8 </td> </tr> <tr> <td> 0x2 </td> <td> Rm </td> <td> 0x1 </td> <td> imm8small </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue imm8small) (set (reg HI h-gr (index-of Rm)) nvalue) (set psw (or (and psw 3996) (or (sll (index-of Rm) 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-movwimm8"></a> <h3>movwimm8 - Move 8-bit immediate</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mov.w Rx,#$imm8</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-imm8 </td> </tr> <tr> <td> 0x4 </td> <td> 0x7 </td> <td> imm8 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((HI nvalue)) (set nvalue imm8) (set (reg HI h-gr Rpsw) nvalue) (set psw (or (and psw 3996) (or (sll Rpsw 12) (or (or (eq (and nvalue 255) 0) (sll HI (eq HI nvalue 0) 1)) (or (sll HI (c-call BI "parity" nvalue) 5) (sll HI (lt QI (srl nvalue (mul 1 8)) 0) 6))))))) </plaintext></font> </li> </ul> <a name="insn-mul"></a> <h3>mul - Multiply</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>mul</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op </td> </tr> <tr> <td> 0xd0 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(sequence ((SI value)) (set value (mul SI (and SI R0 65535) (and SI R2 65535))) (set psw (or (and psw 65436) (or (or (eq (and (trunc HI value) 255) 0) (sll HI (eq HI (trunc HI value) 0) 1)) (or (sll HI (c-call BI "parity" (trunc HI value)) 5) (sll HI (lt QI (srl (trunc HI value) (mul 1 8)) 0) 6))))) (set R0 (trunc HI value)) (set R1 (trunc HI (srl value 16)))) </plaintext></font> </li> </ul> <a name="insn-nop"></a> <h3>nop - nop</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>nop</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 </td> </tr> <tr> <td> f-op </td> </tr> <tr> <td> 0x0 </td> </tr> </table> </li> <br> <li> semantics: <font size=+2> <plaintext>(nop) </plaintext></font> </li> </ul> <a name="insn-notgr"></a> <h3>notgr - NOT general register</h3> <ul> <li> machines: base </li> <br> <li> syntax: <tt><font size=+2>not $Rd</font></tt> </li> <br> <li> format: <table frame=border border=2> <tr> <td> 0 1 2 3 </td> <td> 4 5 6 7 </td> <td> 8 9 10 11 </td> <td> 12 13 14 15 </td> </tr> <tr> <td> f-op1 </td> <td> f-op2 </td> <td> f-op3 </td> <td> f-Rd </td> </tr> <tr> <td> 0x3 </td> <td> 0x0 </td> <td> 0xb </td> <td> Rd </td> </tr

0 1 2 3	4 5 6 7	8 9 10 11	12 13 14 15
f-op1	f-op2	f-Rs	f-Rd
0x4	0xb	Rs	Rd

Instructions

xstormy16 MEM - Memory

xstormy16 ALU - ALU

xstormy16 BR - Branch

xstormy16 xstormy16 - Xstormy16 CPU core

Individual instructions descriptions

adcgrgr - ADD carry and general register to general register