OPENRISC Architecture Documentation

DISCLAIMER: This documentation is derived from the cgen cpu description of this architecture, and does not represent official documentation of the chip maker.

In cgen-parlance, an architecture consists of machines and models. A `machine' is the specification of a variant of the architecture, and a `model' is the implementation of that specification. Typically there is a one-to-one correspondance between machine and model. The distinction allows for separation of what application programs see (the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code. Chip variants that are quite dissimilar can be treated separately by the generated code even though they're both members of the same architecture.

OPENRISC Architecture

This section describes various things about the cgen description of the OPENRISC architecture. Familiarity with cgen cpu descriptions is assumed.

Bit number orientation (arch.lsb0?): lsb = 0

ISA description

CPU Families

Machine variants

openrisc - Generic OpenRISC cpu

or1300 - OpenRISC 1300

Model variants

openrisc-1 - OpenRISC generic model

or1320-1 - OpenRISC 1320 model


h-cbit - condition bit

h-delay-insn - delay insn addr

h-gr - general registers