Instructions

• openrisc - Generic OpenRISC cpu
• MEM - Memory
• ALU - ALU
• BR - Branch
• alphabetically
• or1300 - OpenRISC 1300
• MEM - Memory
• ALU - ALU
• BR - Branch
• alphabetically

openrisc MEM - Memory

• l-lbs - load byte (sign extend)
• l-lbz - load byte (zero extend)
• l-lhs - load halfword (sign extend)
• l-lhz - load halfword (zero extend)
• l-lw - load word
• l-sb - l.sb imm(reg)/reg
• l-sh - l.sh imm(reg)/reg
• l-sw - l.sw imm(reg)/reg

openrisc ALU - ALU

• l-add - l.add reg/reg/reg
• l-addi - l.add reg/reg/lo16
• l-and - l.and reg/reg/reg
• l-andi - l.and reg/reg/lo16
• l-brk - break (exception)
• l-div - divide (signed)
• l-divu - divide (unsigned)
• l-mfsr - mfsr
• l-movhi - movhi
• l-mtsr - mtsr
• l-mul - l.mul reg/reg/reg
• l-muli - l.mul reg/reg/lo16
• l-nop - nop
• l-or - l.or reg/reg/reg
• l-ori - l.or reg/reg/lo16
• l-ror - l.ror reg/reg/reg
• l-rori - l.ror reg/reg/imm
• l-sfeq - l.mnemonic reg/reg
• l-sfeqi - l.mnemonici reg/imm
• l-sfges - l.mnemonic reg/reg
• l-sfgesi - l.mnemonicsi reg/imm
• l-sfgeu - l.mnemonic reg/reg
• l-sfgeui - l.mnemonicui reg/imm
• l-sfgts - l.mnemonic reg/reg
• l-sfgtsi - l.mnemonicsi reg/imm
• l-sfgtu - l.mnemonic reg/reg
• l-sfgtui - l.mnemonicui reg/imm
• l-sfles - l.mnemonic reg/reg
• l-sflesi - l.mnemonicsi reg/imm
• l-sfleu - l.mnemonic reg/reg
• l-sfleui - l.mnemonicui reg/imm
• l-sflts - l.mnemonic reg/reg
• l-sfltsi - l.mnemonicsi reg/imm
• l-sfltu - l.mnemonic reg/reg
• l-sfltui - l.mnemonicui reg/imm
• l-sfne - l.mnemonic reg/reg
• l-sfnei - l.mnemonici reg/imm
• l-sll - l.sll reg/reg/reg
• l-slli - l.sll reg/reg/imm
• l-sra - l.sra reg/reg/reg
• l-srai - l.sra reg/reg/imm
• l-srl - l.srl reg/reg/reg
• l-srli - l.srl reg/reg/imm
• l-sub - l.sub reg/reg/reg
• l-subi - l.sub reg/reg/lo16
• l-xor - l.xor reg/reg/reg
• l-xori - l.xor reg/reg/lo16

openrisc BR - Branch

• l-bal - branch and link (pc relative iaddr)
• l-bf - branch if condition bit is set (pc relative iaddr)
• l-bnf - branch if condition bit not set (pc relative iaddr)
• l-j - jump (absolute iaddr)
• l-jal - jump and link (absolute iaddr)
• l-jalr - jump register and link (absolute iaddr)
• l-jr - jump register (absolute iaddr)
• l-rfe - return from exception
• l-sys - syscall (exception)

openrisc openrisc - Generic OpenRISC cpu

• l-add - l.add reg/reg/reg
• l-addi - l.add reg/reg/lo16
• l-and - l.and reg/reg/reg
• l-andi - l.and reg/reg/lo16
• l-bal - branch and link (pc relative iaddr)
• l-bf - branch if condition bit is set (pc relative iaddr)
• l-bnf - branch if condition bit not set (pc relative iaddr)
• l-brk - break (exception)
• l-div - divide (signed)
• l-divu - divide (unsigned)
• l-j - jump (absolute iaddr)
• l-jal - jump and link (absolute iaddr)
• l-jalr - jump register and link (absolute iaddr)
• l-jr - jump register (absolute iaddr)
• l-lbs - load byte (sign extend)
• l-lbz - load byte (zero extend)
• l-lhs - load halfword (sign extend)
• l-lhz - load halfword (zero extend)
• l-lw - load word
• l-mfsr - mfsr
• l-movhi - movhi
• l-mtsr - mtsr
• l-mul - l.mul reg/reg/reg
• l-muli - l.mul reg/reg/lo16
• l-nop - nop
• l-or - l.or reg/reg/reg
• l-ori - l.or reg/reg/lo16
• l-rfe - return from exception
• l-ror - l.ror reg/reg/reg
• l-rori - l.ror reg/reg/imm
• l-sb - l.sb imm(reg)/reg
• l-sfeq - l.mnemonic reg/reg
• l-sfeqi - l.mnemonici reg/imm
• l-sfges - l.mnemonic reg/reg
• l-sfgesi - l.mnemonicsi reg/imm
• l-sfgeu - l.mnemonic reg/reg
• l-sfgeui - l.mnemonicui reg/imm
• l-sfgts - l.mnemonic reg/reg
• l-sfgtsi - l.mnemonicsi reg/imm
• l-sfgtu - l.mnemonic reg/reg
• l-sfgtui - l.mnemonicui reg/imm
• l-sfles - l.mnemonic reg/reg
• l-sflesi - l.mnemonicsi reg/imm
• l-sfleu - l.mnemonic reg/reg
• l-sfleui - l.mnemonicui reg/imm
• l-sflts - l.mnemonic reg/reg
• l-sfltsi - l.mnemonicsi reg/imm
• l-sfltu - l.mnemonic reg/reg
• l-sfltui - l.mnemonicui reg/imm
• l-sfne - l.mnemonic reg/reg
• l-sfnei - l.mnemonici reg/imm
• l-sh - l.sh imm(reg)/reg
• l-sll - l.sll reg/reg/reg
• l-slli - l.sll reg/reg/imm
• l-sra - l.sra reg/reg/reg
• l-srai - l.sra reg/reg/imm
• l-srl - l.srl reg/reg/reg
• l-srli - l.srl reg/reg/imm
• l-sub - l.sub reg/reg/reg
• l-subi - l.sub reg/reg/lo16
• l-sw - l.sw imm(reg)/reg
• l-sys - syscall (exception)
• l-xor - l.xor reg/reg/reg
• l-xori - l.xor reg/reg/lo16

or1300 MEM - Memory

• l-lbs - load byte (sign extend)
• l-lbz - load byte (zero extend)
• l-lhs - load halfword (sign extend)
• l-lhz - load halfword (zero extend)
• l-lw - load word
• l-sb - l.sb imm(reg)/reg
• l-sh - l.sh imm(reg)/reg
• l-sw - l.sw imm(reg)/reg

or1300 ALU - ALU

• l-add - l.add reg/reg/reg
• l-addi - l.add reg/reg/lo16
• l-and - l.and reg/reg/reg
• l-andi - l.and reg/reg/lo16
• l-brk - break (exception)
• l-div - divide (signed)
• l-divu - divide (unsigned)
• l-mfsr - mfsr
• l-movhi - movhi
• l-mtsr - mtsr
• l-mul - l.mul reg/reg/reg
• l-muli - l.mul reg/reg/lo16
• l-nop - nop
• l-or - l.or reg/reg/reg
• l-ori - l.or reg/reg/lo16
• l-ror - l.ror reg/reg/reg
• l-rori - l.ror reg/reg/imm
• l-sfeq - l.mnemonic reg/reg
• l-sfeqi - l.mnemonici reg/imm
• l-sfges - l.mnemonic reg/reg
• l-sfgesi - l.mnemonicsi reg/imm
• l-sfgeu - l.mnemonic reg/reg
• l-sfgeui - l.mnemonicui reg/imm
• l-sfgts - l.mnemonic reg/reg
• l-sfgtsi - l.mnemonicsi reg/imm
• l-sfgtu - l.mnemonic reg/reg
• l-sfgtui - l.mnemonicui reg/imm
• l-sfles - l.mnemonic reg/reg
• l-sflesi - l.mnemonicsi reg/imm
• l-sfleu - l.mnemonic reg/reg
• l-sfleui - l.mnemonicui reg/imm
• l-sflts - l.mnemonic reg/reg
• l-sfltsi - l.mnemonicsi reg/imm
• l-sfltu - l.mnemonic reg/reg
• l-sfltui - l.mnemonicui reg/imm
• l-sfne - l.mnemonic reg/reg
• l-sfnei - l.mnemonici reg/imm
• l-sll - l.sll reg/reg/reg
• l-slli - l.sll reg/reg/imm
• l-sra - l.sra reg/reg/reg
• l-srai - l.sra reg/reg/imm
• l-srl - l.srl reg/reg/reg
• l-srli - l.srl reg/reg/imm
• l-sub - l.sub reg/reg/reg
• l-subi - l.sub reg/reg/lo16
• l-xor - l.xor reg/reg/reg
• l-xori - l.xor reg/reg/lo16

or1300 BR - Branch

• l-bal - branch and link (pc relative iaddr)
• l-bf - branch if condition bit is set (pc relative iaddr)
• l-bnf - branch if condition bit not set (pc relative iaddr)
• l-j - jump (absolute iaddr)
• l-jal - jump and link (absolute iaddr)
• l-jalr - jump register and link (absolute iaddr)
• l-jr - jump register (absolute iaddr)
• l-rfe - return from exception
• l-sys - syscall (exception)

or1300 or1300 - OpenRISC 1300

• l-add - l.add reg/reg/reg
• l-addi - l.add reg/reg/lo16
• l-and - l.and reg/reg/reg
• l-andi - l.and reg/reg/lo16
• l-bal - branch and link (pc relative iaddr)
• l-bf - branch if condition bit is set (pc relative iaddr)
• l-bnf - branch if condition bit not set (pc relative iaddr)
• l-brk - break (exception)
• l-div - divide (signed)
• l-divu - divide (unsigned)
• l-j - jump (absolute iaddr)
• l-jal - jump and link (absolute iaddr)
• l-jalr - jump register and link (absolute iaddr)
• l-jr - jump register (absolute iaddr)
• l-lbs - load byte (sign extend)
• l-lbz - load byte (zero extend)
• l-lhs - load halfword (sign extend)
• l-lhz - load halfword (zero extend)
• l-lw - load word
• l-mfsr - mfsr
• l-movhi - movhi
• l-mtsr - mtsr
• l-mul - l.mul reg/reg/reg
• l-muli - l.mul reg/reg/lo16
• l-nop - nop
• l-or - l.or reg/reg/reg
• l-ori - l.or reg/reg/lo16
• l-rfe - return from exception
• l-ror - l.ror reg/reg/reg
• l-rori - l.ror reg/reg/imm
• l-sb - l.sb imm(reg)/reg
• l-sfeq - l.mnemonic reg/reg
• l-sfeqi - l.mnemonici reg/imm
• l-sfges - l.mnemonic reg/reg
• l-sfgesi - l.mnemonicsi reg/imm
• l-sfgeu - l.mnemonic reg/reg
• l-sfgeui - l.mnemonicui reg/imm
• l-sfgts - l.mnemonic reg/reg
• l-sfgtsi - l.mnemonicsi reg/imm
• l-sfgtu - l.mnemonic reg/reg
• l-sfgtui - l.mnemonicui reg/imm
• l-sfles - l.mnemonic reg/reg
• l-sflesi - l.mnemonicsi reg/imm
• l-sfleu - l.mnemonic reg/reg
• l-sfleui - l.mnemonicui reg/imm
• l-sflts - l.mnemonic reg/reg
• l-sfltsi - l.mnemonicsi reg/imm
• l-sfltu - l.mnemonic reg/reg
• l-sfltui - l.mnemonicui reg/imm
• l-sfne - l.mnemonic reg/reg
• l-sfnei - l.mnemonici reg/imm
• l-sh - l.sh imm(reg)/reg
• l-sll - l.sll reg/reg/reg
• l-slli - l.sll reg/reg/imm
• l-sra - l.sra reg/reg/reg
• l-srai - l.sra reg/reg/imm
• l-srl - l.srl reg/reg/reg
• l-srli - l.srl reg/reg/imm
• l-sub - l.sub reg/reg/reg
• l-subi - l.sub reg/reg/lo16
• l-sw - l.sw imm(reg)/reg
• l-sys - syscall (exception)
• l-xor - l.xor reg/reg/reg
• l-xori - l.xor reg/reg/lo16

Individual instructions descriptions

l-add - l.add reg/reg/reg

• machines: base


• syntax: l.add $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-7	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x0



• semantics:

  (set rD (add rA rB))
  

l-addi - l.add reg/reg/lo16

• machines: base


• syntax: l.addi $rD,$rA,$lo16


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-lo16
  0x2	0x5	rD	rA	lo16



• semantics:

  (set rD (add rA lo16))
  

l-and - l.and reg/reg/reg

• machines: base


• syntax: l.and $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-7	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x3



• semantics:

  (set rD (and rA rB))
  

l-andi - l.and reg/reg/lo16

• machines: base


• syntax: l.andi $rD,$rA,$lo16


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-lo16
  0x2	0x8	rD	rA	lo16



• semantics:

  (set rD (and rA (and lo16 65535)))
  

l-bal - branch and link (pc relative iaddr)

• machines: base


• syntax: l.bal ${disp-26}


• format:

  31 30	29 28 27 26	25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-disp26
  0x0	0x2	disp-26



• semantics:

  (sequence
    ()
    (set (reg h-gr 11) (add (reg h-delay-insn) 4))
    (delay 1 (set pc disp-26)))
  

l-bf - branch if condition bit is set (pc relative iaddr)

• machines: base


• syntax: l.bf ${disp-26}


• format:

  31 30	29 28 27 26	25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-disp26
  0x0	0x4	disp-26



• semantics:

  (if (eq cbit 1)
      (sequence () (delay 1 (set pc disp-26))))
  

l-bnf - branch if condition bit not set (pc relative iaddr)

• machines: base


• syntax: l.bnf ${disp-26}


• format:

  31 30	29 28 27 26	25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-disp26
  0x0	0x3	disp-26



• semantics:

  (if (eq cbit 0)
      (sequence () (delay 1 (set pc disp-26))))
  

l-brk - break (exception)

• machines: base


• syntax: l.brk ${uimm-16}


• format:

  31 30	29 28 27 26	25 24	23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op3	f-op4	f-r2	f-uimm16
  0x0	0x5	0x3	0x0	rA	uimm-16



• semantics:

  (c-call VOID "@cpu@_cpu_brk" uimm-16)
  

l-div - divide (signed)

• machines: base


• syntax: l.div $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-7	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x9



• semantics:

  (if VOID
      (eq rB 0)
      (c-call
        VOID
        "@arch@_cpu_trap"
        pc
        (enum SI E_ILLEGAL))
      (set rD (div rA rB)))
  

l-divu - divide (unsigned)

• machines: base


• syntax: l.divu $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-7	f-op7
  0x3	0x8	rD	rA	rB	0x0	0xa



• semantics:

  (if VOID
      (eq rB 0)
      (c-call
        VOID
        "@arch@_cpu_trap"
        pc
        (enum SI E_ILLEGAL))
      (set rD (udiv rA rB)))
  

l-j - jump (absolute iaddr)

• machines: base


• syntax: l.j ${abs-26}


• format:

  31 30	29 28 27 26	25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-abs26
  0x0	0x0	abs-26



• semantics:

  (delay 1 (set pc abs-26))
  

l-jal - jump and link (absolute iaddr)

• machines: base


• syntax: l.jal ${abs-26}


• format:

  31 30	29 28 27 26	25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-abs26
  0x0	0x1	abs-26



• semantics:

  (sequence
    ()
    (set (reg h-gr 11) (add (reg h-delay-insn) 4))
    (delay 1 (set pc abs-26)))
  

l-jalr - jump register and link (absolute iaddr)

• machines: base


• syntax: l.jalr $rA


• format:

  31 30	29 28 27 26	25 24	23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op3	f-op4	f-r2	f-uimm16
  0x0	0x5	0x0	0x1	rA	uimm-16



• semantics:

  (sequence
    ((WI tmp-slot))
    (set tmp-slot rA)
    (set (reg h-gr 11) (add (reg h-delay-insn) 4))
    (delay 1 (set pc tmp-slot)))
  

l-jr - jump register (absolute iaddr)

• machines: base


• syntax: l.jr $rA


• format:

  31 30	29 28 27 26	25 24	23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op3	f-op4	f-r2	f-uimm16
  0x0	0x5	0x0	0x0	rA	uimm-16



• semantics:

  (delay 1 (set pc rA))
  

l-lbs - load byte (sign extend)

• machines: base


• syntax: l.lbs $rD,${simm-16}($rA)


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-simm16
  0x2	0x2	rD	rA	simm-16



• semantics:

  (set rD (ext SI (mem QI (add rA simm-16))))
  

l-lbz - load byte (zero extend)

• machines: base


• syntax: l.lbz $rD,${simm-16}($rA)


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-simm16
  0x2	0x1	rD	rA	simm-16



• semantics:

  (set rD (zext SI (mem QI (add rA simm-16))))
  

l-lhs - load halfword (sign extend)

• machines: base


• syntax: l.lhs $rD,${simm-16}($rA)


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-simm16
  0x2	0x4	rD	rA	simm-16



• semantics:

  (set rD (ext SI (mem HI (add rA simm-16))))
  

l-lhz - load halfword (zero extend)

• machines: base


• syntax: l.lhz $rD,${simm-16}($rA)


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-simm16
  0x2	0x3	rD	rA	simm-16



• semantics:

  (set rD (zext SI (mem HI (add rA simm-16))))
  

l-lw - load word

• machines: base


• syntax: l.lw $rD,${simm-16}($rA)


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-simm16
  0x2	0x0	rD	rA	simm-16



• semantics:

  (set rD (mem SI (add rA simm-16)))
  

l-mfsr - mfsr

• machines: base


• syntax: l.mfsr $rD,$rA


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-uimm16
  0x0	0x7	rD	rA	uimm-16



• semantics:

  (set rD (c-call SI "@cpu@_cpu_mfsr" rA))
  

l-movhi - movhi

• machines: base


• syntax: l.movhi $rD,$hi16


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-simm16
  0x0	0x6	rD	rA	hi16



• semantics:

  (set rD (sll WI hi16 16))
  

l-mtsr - mtsr

• machines: base


• syntax: l.mtsr $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-i16-1
  0x1	0x0	rD	rA	rB	0x0



• semantics:

  (c-call VOID "@cpu@_cpu_mtsr" rA rB)
  

l-mul - l.mul reg/reg/reg

• machines: base


• syntax: l.mul $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-7	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x6



• semantics:

  (set rD (mul rA rB))
  

l-muli - l.mul reg/reg/lo16

• machines: base


• syntax: l.muli $rD,$rA,$lo16


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-lo16
  0x2	0xb	rD	rA	lo16



• semantics:

  (set rD (mul rA (and lo16 65535)))
  

l-nop - nop

• machines: base


• syntax: l.nop


• format:

  31 30	29 28 27 26	25 24	23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op3	f-op4	f-r2	f-uimm16
  0x0	0x5	0x1	0x0	rA	uimm-16



• semantics:

  (nop)
  

l-or - l.or reg/reg/reg

• machines: base


• syntax: l.or $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-7	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x4



• semantics:

  (set rD (or rA rB))
  

l-ori - l.or reg/reg/lo16

• machines: base


• syntax: l.ori $rD,$rA,$lo16


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-lo16
  0x2	0x9	rD	rA	lo16



• semantics:

  (set rD (or rA (and lo16 65535)))
  

l-rfe - return from exception

• machines: base


• syntax: l.rfe $rA


• format:

  31 30	29 28 27 26	25 24	23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op3	f-op4	f-r2	f-uimm16
  0x0	0x5	0x0	0x2	rA	uimm-16



• semantics:

  (sequence
    ()
    (delay 1 (set pc (c-call SI "@cpu@_cpu_rfe" rA))))
  

l-ror - l.ror reg/reg/reg

• machines: base


• syntax: l.ror $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5	4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-3	f-op6	f-f-4-1	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x4	0x0	0x8



• semantics:

  (set rD (ror rA rB))
  

l-rori - l.ror reg/reg/imm

• machines: base


• syntax: l.rori $rD,$rA,${uimm-5}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8	7 6 5	4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-f-15-8	f-op6	f-uimm5
  0x2	0xd	rD	rA	0x0	0x4	uimm-5



• semantics:

  (set rD (ror rA uimm-5))
  

l-sb - l.sb imm(reg)/reg

• machines: base


• syntax: l.sb ${ui16nc}($rA),$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r3	f-i16nc
  0x3	0x6	rD	rB	ui16nc



• semantics:

  (set (mem QI (add rA ui16nc)) rB)
  

l-sfeq - l.mnemonic reg/reg

• machines: base


• syntax: l.sfeq $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-r3	f-f-10-11
  0x3	0x9	0x0	rA	rB	0x0



• semantics:

  (set cbit (eq rA rB))
  

l-sfeqi - l.mnemonici reg/imm

• machines: base


• syntax: l.sfeqi $rA,${simm-16}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-simm16
  0x2	0xe	0x0	rA	simm-16



• semantics:

  (set cbit (eq rA simm-16))
  

l-sfges - l.mnemonic reg/reg

• machines: base


• syntax: l.sfges $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-r3	f-f-10-11
  0x3	0x9	0x7	rA	rB	0x0



• semantics:

  (set cbit (ge rA rB))
  

l-sfgesi - l.mnemonicsi reg/imm

• machines: base


• syntax: l.sfgesi $rA,${simm-16}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-simm16
  0x2	0xe	0x7	rA	simm-16



• semantics:

  (set cbit (ge rA simm-16))
  

l-sfgeu - l.mnemonic reg/reg

• machines: base


• syntax: l.sfgeu $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-r3	f-f-10-11
  0x3	0x9	0x3	rA	rB	0x0



• semantics:

  (set cbit (ge rA rB))
  

l-sfgeui - l.mnemonicui reg/imm

• machines: base


• syntax: l.sfgeui $rA,${uimm-16}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-uimm16
  0x2	0xe	0x3	rA	uimm-16



• semantics:

  (set cbit (ge rA uimm-16))
  

l-sfgts - l.mnemonic reg/reg

• machines: base


• syntax: l.sfgts $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-r3	f-f-10-11
  0x3	0x9	0x6	rA	rB	0x0



• semantics:

  (set cbit (gt rA rB))
  

l-sfgtsi - l.mnemonicsi reg/imm

• machines: base


• syntax: l.sfgtsi $rA,${simm-16}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-simm16
  0x2	0xe	0x6	rA	simm-16



• semantics:

  (set cbit (gt rA simm-16))
  

l-sfgtu - l.mnemonic reg/reg

• machines: base


• syntax: l.sfgtu $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-r3	f-f-10-11
  0x3	0x9	0x2	rA	rB	0x0



• semantics:

  (set cbit (gt rA rB))
  

l-sfgtui - l.mnemonicui reg/imm

• machines: base


• syntax: l.sfgtui $rA,${uimm-16}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-uimm16
  0x2	0xe	0x2	rA	uimm-16



• semantics:

  (set cbit (gt rA uimm-16))
  

l-sfles - l.mnemonic reg/reg

• machines: base


• syntax: l.sfles $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-r3	f-f-10-11
  0x3	0x9	0x9	rA	rB	0x0



• semantics:

  (set cbit (le rA rB))
  

l-sflesi - l.mnemonicsi reg/imm

• machines: base


• syntax: l.sflesi $rA,${simm-16}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-simm16
  0x2	0xe	0x9	rA	simm-16



• semantics:

  (set cbit (le rA simm-16))
  

l-sfleu - l.mnemonic reg/reg

• machines: base


• syntax: l.sfleu $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-r3	f-f-10-11
  0x3	0x9	0x5	rA	rB	0x0



• semantics:

  (set cbit (le rA rB))
  

l-sfleui - l.mnemonicui reg/imm

• machines: base


• syntax: l.sfleui $rA,${uimm-16}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-uimm16
  0x2	0xe	0x5	rA	uimm-16



• semantics:

  (set cbit (le rA uimm-16))
  

l-sflts - l.mnemonic reg/reg

• machines: base


• syntax: l.sflts $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-r3	f-f-10-11
  0x3	0x9	0x8	rA	rB	0x0



• semantics:

  (set cbit (lt rA rB))
  

l-sfltsi - l.mnemonicsi reg/imm

• machines: base


• syntax: l.sfltsi $rA,${simm-16}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-simm16
  0x2	0xe	0x8	rA	simm-16



• semantics:

  (set cbit (lt rA simm-16))
  

l-sfltu - l.mnemonic reg/reg

• machines: base


• syntax: l.sfltu $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-r3	f-f-10-11
  0x3	0x9	0x4	rA	rB	0x0



• semantics:

  (set cbit (lt rA rB))
  

l-sfltui - l.mnemonicui reg/imm

• machines: base


• syntax: l.sfltui $rA,${uimm-16}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-uimm16
  0x2	0xe	0x4	rA	uimm-16



• semantics:

  (set cbit (lt rA uimm-16))
  

l-sfne - l.mnemonic reg/reg

• machines: base


• syntax: l.sfne $rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-r3	f-f-10-11
  0x3	0x9	0x1	rA	rB	0x0



• semantics:

  (set cbit (ne rA rB))
  

l-sfnei - l.mnemonici reg/imm

• machines: base


• syntax: l.sfnei $rA,${simm-16}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op5	f-r2	f-simm16
  0x2	0xe	0x1	rA	simm-16



• semantics:

  (set cbit (ne rA simm-16))
  

l-sh - l.sh imm(reg)/reg

• machines: base


• syntax: l.sh ${ui16nc}($rA),$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r3	f-i16nc
  0x3	0x7	rD	rB	ui16nc



• semantics:

  (set (mem HI (add rA ui16nc)) rB)
  

l-sll - l.sll reg/reg/reg

• machines: base


• syntax: l.sll $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5	4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-3	f-op6	f-f-4-1	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x0	0x0	0x8



• semantics:

  (set rD (sll rA rB))
  

l-slli - l.sll reg/reg/imm

• machines: base


• syntax: l.slli $rD,$rA,${uimm-5}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8	7 6 5	4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-f-15-8	f-op6	f-uimm5
  0x2	0xd	rD	rA	0x0	0x0	uimm-5



• semantics:

  (set rD (sll rA uimm-5))
  

l-sra - l.sra reg/reg/reg

• machines: base


• syntax: l.sra $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5	4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-3	f-op6	f-f-4-1	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x2	0x0	0x8



• semantics:

  (set rD (sra rA rB))
  

l-srai - l.sra reg/reg/imm

• machines: base


• syntax: l.srai $rD,$rA,${uimm-5}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8	7 6 5	4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-f-15-8	f-op6	f-uimm5
  0x2	0xd	rD	rA	0x0	0x2	uimm-5



• semantics:

  (set rD (sra rA uimm-5))
  

l-srl - l.srl reg/reg/reg

• machines: base


• syntax: l.srl $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5	4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-3	f-op6	f-f-4-1	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x1	0x0	0x8



• semantics:

  (set rD (srl rA rB))
  

l-srli - l.srl reg/reg/imm

• machines: base


• syntax: l.srli $rD,$rA,${uimm-5}


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8	7 6 5	4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-f-15-8	f-op6	f-uimm5
  0x2	0xd	rD	rA	0x0	0x1	uimm-5



• semantics:

  (set rD (srl rA uimm-5))
  

l-sub - l.sub reg/reg/reg

• machines: base


• syntax: l.sub $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-7	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x2



• semantics:

  (set rD (sub rA rB))
  

l-subi - l.sub reg/reg/lo16

• machines: base


• syntax: l.subi $rD,$rA,$lo16


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-lo16
  0x2	0x7	rD	rA	lo16



• semantics:

  (set rD (sub rA lo16))
  

l-sw - l.sw imm(reg)/reg

• machines: base


• syntax: l.sw ${ui16nc}($rA),$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r3	f-i16nc
  0x3	0x5	rD	rB	ui16nc



• semantics:

  (set (mem SI (add rA ui16nc)) rB)
  

l-sys - syscall (exception)

• machines: base


• syntax: l.sys ${uimm-16}


• format:

  31 30	29 28 27 26	25 24	23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-op3	f-op4	f-r2	f-uimm16
  0x0	0x5	0x2	0x0	rA	uimm-16



• semantics:

  (sequence
    ()
    (delay 1
           (set pc
                (c-call SI "@cpu@_except" pc 3072 uimm-16))))
  

l-xor - l.xor reg/reg/reg

• machines: base


• syntax: l.xor $rD,$rA,$rB


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-r3	f-f-10-7	f-op7
  0x3	0x8	rD	rA	rB	0x0	0x5



• semantics:

  (set rD (xor rA rB))
  

l-xori - l.xor reg/reg/lo16

• machines: base


• syntax: l.xori $rD,$rA,$lo16


• format:

  31 30	29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-class	f-sub	f-r1	f-r2	f-lo16
  0x2	0xa	rD	rA	lo16



• semantics:

  (set rD (xor rA (and lo16 65535)))
  

Macro Instructions

• openrisc - Generic OpenRISC cpu
• or1300 - OpenRISC 1300

openrisc - Generic OpenRISC cpu

• l-ret - ret

or1300 - OpenRISC 1300

• l-ret - ret

Individual macro-instructions descriptions

l-ret - ret

• syntax: l.ret


• transformation:

  ((emit l-jr (rA 11) (uimm-16 0)))
  

This documentation was machine generated from the cgen cpu description files for this architecture.
http://sources.redhat.com/cgen/