Instructions

Instructions for each machine:

openrisc MEM - Memory


openrisc ALU - ALU


openrisc BR - Branch


openrisc openrisc - Generic OpenRISC cpu


or1300 MEM - Memory


or1300 ALU - ALU


or1300 BR - Branch


or1300 or1300 - OpenRISC 1300


Individual instructions descriptions


l-add - l.add reg/reg/reg

l-addi - l.add reg/reg/lo16

l-and - l.and reg/reg/reg

l-andi - l.and reg/reg/lo16

l-bal - branch and link (pc relative iaddr)

l-bf - branch if condition bit is set (pc relative iaddr)

l-bnf - branch if condition bit not set (pc relative iaddr)

l-brk - break (exception)

l-div - divide (signed)

l-divu - divide (unsigned)

l-j - jump (absolute iaddr)

l-jal - jump and link (absolute iaddr)

l-jalr - jump register and link (absolute iaddr)

l-jr - jump register (absolute iaddr)

l-lbs - load byte (sign extend)

l-lbz - load byte (zero extend)

l-lhs - load halfword (sign extend)

l-lhz - load halfword (zero extend)

l-lw - load word

l-mfsr - mfsr

l-movhi - movhi

l-mtsr - mtsr

l-mul - l.mul reg/reg/reg

l-muli - l.mul reg/reg/lo16

l-nop - nop

l-or - l.or reg/reg/reg

l-ori - l.or reg/reg/lo16

l-rfe - return from exception

l-ror - l.ror reg/reg/reg

l-rori - l.ror reg/reg/imm

l-sb - l.sb imm(reg)/reg

l-sfeq - l.mnemonic reg/reg

l-sfeqi - l.mnemonici reg/imm

l-sfges - l.mnemonic reg/reg

l-sfgesi - l.mnemonicsi reg/imm

l-sfgeu - l.mnemonic reg/reg

l-sfgeui - l.mnemonicui reg/imm

l-sfgts - l.mnemonic reg/reg

l-sfgtsi - l.mnemonicsi reg/imm

l-sfgtu - l.mnemonic reg/reg

l-sfgtui - l.mnemonicui reg/imm

l-sfles - l.mnemonic reg/reg

l-sflesi - l.mnemonicsi reg/imm

l-sfleu - l.mnemonic reg/reg

l-sfleui - l.mnemonicui reg/imm

l-sflts - l.mnemonic reg/reg

l-sfltsi - l.mnemonicsi reg/imm

l-sfltu - l.mnemonic reg/reg

l-sfltui - l.mnemonicui reg/imm

l-sfne - l.mnemonic reg/reg

l-sfnei - l.mnemonici reg/imm

l-sh - l.sh imm(reg)/reg

l-sll - l.sll reg/reg/reg

l-slli - l.sll reg/reg/imm

l-sra - l.sra reg/reg/reg

l-srai - l.sra reg/reg/imm

l-srl - l.srl reg/reg/reg

l-srli - l.srl reg/reg/imm

l-sub - l.sub reg/reg/reg

l-subi - l.sub reg/reg/lo16

l-sw - l.sw imm(reg)/reg

l-sys - syscall (exception)

l-xor - l.xor reg/reg/reg

l-xori - l.xor reg/reg/lo16


Macro Instructions

Macro instructions for each machine:

openrisc - Generic OpenRISC cpu

or1300 - OpenRISC 1300

Individual macro-instructions descriptions


l-ret - ret


This documentation was machine generated from the cgen cpu description files for this architecture.
http://sources.redhat.com/cgen/