0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0xa | sr |
(set dr (add dr sr))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x8 | dr | 0xa | sr | slo16 |
(set dr (add sr slo16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-r1 | f-simm8 |
0x4 | dr | simm8 |
(set dr (add dr simm8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0x8 | sr |
(parallel () (set dr (add dr sr)) (set condbit (add-oflag dr sr 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x8 | dr | 0x8 | sr | simm16 |
(parallel () (set dr (add sr simm16)) (set condbit (add-oflag sr simm16 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0x9 | sr |
(parallel () (set dr (addc dr sr condbit)) (set condbit (add-cflag dr sr condbit)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0xc | sr |
(set dr (and dr sr))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-uimm16 |
0x8 | dr | 0xc | sr | uimm16 |
(set dr (and sr uimm16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-disp24 |
0xf | 0xc | disp24 |
(if condbit (set pc disp24))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-r1 | f-disp8 |
0x7 | 0xc | disp8 |
(if condbit (set pc disp8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-disp24 |
0xf | 0x8 | disp24 |
(if condbit (sequence () (set (reg h-gr 14) (add pc 4)) (set pc disp24)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-r1 | f-disp8 |
0x7 | 0x8 | disp8 |
(if condbit (sequence () (set (reg h-gr 14) (add (and pc -4) 4)) (set pc disp8)))
0 1 2 3 | 4 | 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-bit4 | f-uimm3 | f-op2 | f-r2 | f-simm16 |
0xa | 0x0 | uimm3 | 0x7 | sr | slo16 |
(set QI (mem QI (add sr slo16)) (and QI (mem QI (add sr slo16)) (inv QI (sll USI 1 (sub 7 uimm3)))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-disp16 |
0xb | src1 | 0x0 | src2 | disp16 |
(if (eq src1 src2) (set pc disp16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-disp16 |
0xb | 0x0 | 0x8 | src2 | disp16 |
(if (eq src2 0) (set pc disp16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-disp16 |
0xb | 0x0 | 0xb | src2 | disp16 |
(if (ge src2 0) (set pc disp16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-disp16 |
0xb | 0x0 | 0xd | src2 | disp16 |
(if (gt src2 0) (set pc disp16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-disp24 |
0xf | 0xe | disp24 |
(sequence () (set (reg h-gr 14) (add pc 4)) (set pc disp24))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-r1 | f-disp8 |
0x7 | 0xe | disp8 |
(sequence () (set (reg h-gr 14) (add (and pc -4) 4)) (set pc disp8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-disp16 |
0xb | 0x0 | 0xc | src2 | disp16 |
(if (le src2 0) (set pc disp16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-disp16 |
0xb | 0x0 | 0xa | src2 | disp16 |
(if (lt src2 0) (set pc disp16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-disp24 |
0xf | 0xd | disp24 |
(if (not condbit) (set pc disp24))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-r1 | f-disp8 |
0x7 | 0xd | disp8 |
(if (not condbit) (set pc disp8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-disp24 |
0xf | 0x9 | disp24 |
(if (not condbit) (sequence () (set (reg h-gr 14) (add pc 4)) (set pc disp24)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-r1 | f-disp8 |
0x7 | 0x9 | disp8 |
(if (not condbit) (sequence () (set (reg h-gr 14) (add (and pc -4) 4)) (set pc disp8)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-disp16 |
0xb | src1 | 0x1 | src2 | disp16 |
(if (ne src1 src2) (set pc disp16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-disp16 |
0xb | 0x0 | 0x9 | src2 | disp16 |
(if (ne src2 0) (set pc disp16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-disp24 |
0xf | 0xf | disp24 |
(set pc disp24)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-r1 | f-disp8 |
0x7 | 0xf | disp8 |
(set pc disp8)
0 1 2 3 | 4 | 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-bit4 | f-uimm3 | f-op2 | f-r2 | f-simm16 |
0xa | 0x0 | uimm3 | 0x6 | sr | slo16 |
(set QI (mem QI (add sr slo16)) (or QI (mem QI (add sr slo16)) (sll USI 1 (sub 7 uimm3))))
0 1 2 3 | 4 | 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-bit4 | f-uimm3 | f-op2 | f-r2 |
0x0 | 0x0 | uimm3 | 0xf | sr |
(set condbit (and QI (srl USI sr (sub 7 uimm3)) 1))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-r1 | f-uimm8 |
0x7 | 0x2 | uimm8 |
(set USI (reg h-cr 0) (and USI (reg h-cr 0) (or USI (inv BI uimm8) 65280)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | src1 | 0x4 | src2 |
(set condbit (lt src1 src2))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | src1 | 0x6 | src2 |
(set condbit (eq src1 src2))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x8 | 0x0 | 0x4 | src2 | simm16 |
(set condbit (lt src2 simm16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | src1 | 0x5 | src2 |
(set condbit (ltu src1 src2))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x8 | 0x0 | 0x5 | src2 | simm16 |
(set condbit (ltu src2 simm16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | 0x0 | 0x7 | src2 |
(set condbit (eq src2 0))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x0 | sr | 0x0 |
(if (ne sr 0) (set dr (div dr sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x0 | sr | 0x18 |
(if (ne sr 0) (set dr (div (ext WI (trunc BI dr)) sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x0 | sr | 0x10 |
(if (ne sr 0) (set dr (div (ext WI (trunc HI dr)) sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x1 | sr | 0x0 |
(if (ne sr 0) (set dr (udiv dr sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x1 | sr | 0x18 |
(if (ne sr 0) (set dr (udiv dr sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x1 | sr | 0x10 |
(if (ne sr 0) (set dr (udiv dr sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | 0xc | 0xc | sr |
(if condbit (set pc (and sr -4)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | 0xe | 0xc | sr |
(parallel () (set (reg h-gr 14) (add (and pc -4) 4)) (set pc (and sr -4)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | 0xf | 0xc | sr |
(set pc (and sr -4))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | 0xd | 0xc | sr |
(if (not condbit) (set pc (and sr -4)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | dr | 0xc | sr |
(set dr (mem WI sr))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0xa | dr | 0xc | sr | slo16 |
(set dr (mem WI (add sr slo16)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | dr | 0xe | sr |
(parallel () (set dr (mem WI sr)) (set sr (add sr 4)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-uimm24 |
0xe | dr | uimm24 |
(set dr uimm24)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | dr | 0x8 | sr |
(set dr (ext WI (mem QI sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0xa | dr | 0x8 | sr | slo16 |
(set dr (ext WI (mem QI (add sr slo16))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | dr | 0xa | sr |
(set dr (ext WI (mem HI sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0xa | dr | 0xa | sr | slo16 |
(set dr (ext WI (mem HI (add sr slo16))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0xf | 0x0 | slo16 |
(set dr slo16)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-r1 | f-simm8 |
0x6 | dr | simm8 |
(set dr simm8)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | dr | 0x9 | sr |
(set dr (zext WI (mem QI sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0xa | dr | 0x9 | sr | slo16 |
(set dr (zext WI (mem QI (add sr slo16))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | dr | 0xb | sr |
(set dr (zext WI (mem HI sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0xa | dr | 0xb | sr | slo16 |
(set dr (zext WI (mem HI (add sr slo16))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | dr | 0xd | sr |
(sequence () (set (reg h-lock) 1) (set dr (mem WI sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x3 | src1 | 0x4 | src2 |
(set accum (sra DI (sll DI (add DI accum (mul DI (ext DI (and WI src1 4294901760)) (ext DI (trunc HI (sra WI src2 16))))) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 | 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-acc | f-op23 | f-r2 |
0x3 | src1 | acc | 0x4 | src2 |
(set acc (sra DI (sll DI (add DI acc (mul DI (ext DI (and WI src1 4294901760)) (ext DI (trunc HI (sra WI src2 16))))) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | src1 | 0xc | src2 |
(set (reg h-accums 1) (sra DI (sll DI (add DI (reg h-accums 1) (sll DI (ext DI (mul SI (ext SI (trunc HI src1)) (sra SI src2 16))) 16)) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x3 | src1 | 0x5 | src2 |
(set accum (sra DI (sll DI (add DI accum (mul DI (ext DI (sll WI src1 16)) (ext DI (trunc HI src2)))) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 | 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-acc | f-op23 | f-r2 |
0x3 | src1 | acc | 0x5 | src2 |
(set acc (sra DI (sll DI (add DI acc (mul DI (ext DI (sll WI src1 16)) (ext DI (trunc HI src2)))) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x3 | src1 | 0x6 | src2 |
(set accum (sra DI (sll DI (add DI accum (mul DI (ext DI src1) (ext DI (trunc HI (sra WI src2 16))))) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 | 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-acc | f-op23 | f-r2 |
0x3 | src1 | acc | 0x6 | src2 |
(set acc (add acc (mul (ext DI src1) (ext DI (trunc HI (sra src2 16))))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x3 | src1 | 0x7 | src2 |
(set accum (sra DI (sll DI (add DI accum (mul DI (ext DI src1) (ext DI (trunc HI src2)))) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 | 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-acc | f-op23 | f-r2 |
0x3 | src1 | acc | 0x7 | src2 |
(set acc (add acc (mul (ext DI src1) (ext DI (trunc HI src2)))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | src1 | 0xb | src2 |
(set (reg h-accums 1) (sra DI (sll DI (add DI (reg h-accums 1) (mul DI (ext DI src1) (ext DI (and src2 65535)))) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | src1 | 0xd | src2 |
(set accum (sra DI (sll DI (sub accum (sra DI (sll DI (mul DI (ext DI (trunc HI src1)) (ext DI (trunc HI src2))) 32) 16)) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | dr | 0x6 | sr |
(set dr (mul dr sr))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x3 | src1 | 0x0 | src2 |
(set accum (sra DI (sll DI (mul DI (ext DI (and WI src1 4294901760)) (ext DI (trunc HI (sra WI src2 16)))) 16) 16))
0 1 2 3 | 4 5 6 7 | 8 | 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-acc | f-op23 | f-r2 |
0x3 | src1 | acc | 0x0 | src2 |
(set acc (sra DI (sll DI (mul DI (ext DI (and WI src1 4294901760)) (ext DI (trunc HI (sra WI src2 16)))) 16) 16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x3 | src1 | 0x1 | src2 |
(set accum (sra DI (sll DI (mul DI (ext DI (sll WI src1 16)) (ext DI (trunc HI src2))) 16) 16))
0 1 2 3 | 4 5 6 7 | 8 | 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-acc | f-op23 | f-r2 |
0x3 | src1 | acc | 0x1 | src2 |
(set acc (sra DI (sll DI (mul DI (ext DI (sll WI src1 16)) (ext DI (trunc HI src2))) 16) 16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x3 | src1 | 0x2 | src2 |
(set accum (sra DI (sll DI (mul DI (ext DI src1) (ext DI (trunc HI (sra WI src2 16)))) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 | 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-acc | f-op23 | f-r2 |
0x3 | src1 | acc | 0x2 | src2 |
(set acc (mul (ext DI src1) (ext DI (trunc HI (sra src2 16)))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x3 | src1 | 0x3 | src2 |
(set accum (sra DI (sll DI (mul DI (ext DI src1) (ext DI (trunc HI src2))) 8) 8))
0 1 2 3 | 4 5 6 7 | 8 | 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-acc | f-op23 | f-r2 |
0x3 | src1 | acc | 0x3 | src2 |
(set acc (mul (ext DI src1) (ext DI (trunc HI src2))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | src1 | 0xa | src2 |
(set (reg h-accums 1) (sra DI (sll DI (mul DI (ext DI src1) (ext DI (and src2 65535))) 16) 16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | dr | 0x8 | sr |
(set dr sr)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | dr | 0xf | 0x0 |
(set dr (trunc WI (sra DI accum 32)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 | 14 15 |
f-op1 | f-r1 | f-op2 | f-accs | f-op3 |
0x5 | dr | 0xf | accs | 0x0 |
(set dr (trunc WI (sra DI accs 32)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | dr | 0xf | 0x1 |
(set dr (trunc WI accum))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 | 14 15 |
f-op1 | f-r1 | f-op2 | f-accs | f-op3 |
0x5 | dr | 0xf | accs | 0x1 |
(set dr (trunc WI accs))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | dr | 0xf | 0x2 |
(set dr (trunc WI (sra DI accum 16)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 | 14 15 |
f-op1 | f-r1 | f-op2 | f-accs | f-op3 |
0x5 | dr | 0xf | accs | 0x2 |
(set dr (trunc WI (sra DI accs 16)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | dr | 0x9 | scr |
(set dr scr)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | src1 | 0x7 | 0x0 |
(set accum (or DI (and DI accum 4294967295) (sll DI (ext DI src1) 32)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 | 14 15 |
f-op1 | f-r1 | f-op2 | f-accs | f-op3 |
0x5 | src1 | 0x7 | accs | 0x0 |
(set accs (or DI (and DI accs 4294967295) (sll DI (ext DI src1) 32)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | src1 | 0x7 | 0x1 |
(set accum (or DI (and DI accum 18446744069414584320) (zext DI src1)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 | 14 15 |
f-op1 | f-r1 | f-op2 | f-accs | f-op3 |
0x5 | src1 | 0x7 | accs | 0x1 |
(set accs (or DI (and DI accs 18446744069414584320) (zext DI src1)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | dcr | 0xa | sr |
(set dcr sr)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0x3 | sr |
(set dr (neg sr))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x7 | 0x0 | 0x0 | 0x0 |
(c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); ")
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0xb | sr |
(set dr (inv sr))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0xe | sr |
(set dr (or dr sr))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-uimm16 |
0x8 | dr | 0xe | sr | ulo16 |
(set dr (or sr ulo16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | 0x3 | 0x7 | src2 |
(set condbit (cond BI ((eq (and src2 255) 0) 1) ((eq (and src2 65280) 0) 1) ((eq (and src2 16711680) 0) 1) ((eq (and src2 4278190080) 0) 1) (else . 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | 0x0 | 0x9 | 0x0 |
(sequence ((DI tmp1)) (set tmp1 (sll DI accum 1)) (set tmp1 (add DI tmp1 32768)) (set accum (cond DI ((gt tmp1 140737488289792) 140737488289792) ((lt tmp1 18446603336221196288) 18446603336221196288) (else and tmp1 18446744073709486080))))
0 1 2 3 | 4 5 | 6 7 | 8 9 10 11 | 12 13 | 14 | 15 |
f-op1 | f-accd | f-bits67 | f-op2 | f-accs | f-bit14 | f-imm1 |
0x5 | accd | 0x0 | 0x9 | accs | 0x0 | imm1 |
(sequence ((DI tmp1)) (set tmp1 (sll accs imm1)) (set tmp1 (add tmp1 32768)) (set accd (cond DI ((gt tmp1 140737488289792) 140737488289792) ((lt tmp1 18446603336221196288) 18446603336221196288) (else and tmp1 18446744073709486080))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | 0x0 | 0x8 | 0x0 |
(sequence ((DI tmp1)) (set tmp1 (and accum 72057594037927935)) (if (andif (ge tmp1 70366596694016) (le tmp1 36028797018963967)) (set tmp1 70366596694016) (if (andif (ge tmp1 36028797018963968) (le tmp1 71987225293750272)) (set tmp1 71987225293750272) (set tmp1 (and (add accum 1073741824) 18446744071562067968)))) (set tmp1 (sll tmp1 1)) (set accum (sra DI (sll DI tmp1 7) 7)))
0 1 2 3 | 4 5 | 6 7 | 8 9 10 11 | 12 13 | 14 | 15 |
f-op1 | f-accd | f-bits67 | f-op2 | f-accs | f-bit14 | f-imm1 |
0x5 | accd | 0x0 | 0x8 | accs | 0x0 | imm1 |
(sequence ((DI tmp1)) (set tmp1 (sll accs imm1)) (set tmp1 (add tmp1 2147483648)) (set accd (cond DI ((gt tmp1 140733193388032) 140733193388032) ((lt tmp1 18446603336221196288) 18446603336221196288) (else and tmp1 18446744069414584320))))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x2 | sr | 0x0 |
(if (ne sr 0) (set dr (mod dr sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x2 | sr | 0x18 |
(if (ne sr 0) (set dr (mod (ext WI (trunc BI dr)) sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x2 | sr | 0x10 |
(if (ne sr 0) (set dr (mod (ext WI (trunc HI dr)) sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x3 | sr | 0x0 |
(if (ne sr 0) (set dr (umod dr sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x3 | sr | 0x18 |
(if (ne sr 0) (set dr (umod dr sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x3 | sr | 0x10 |
(if (ne sr 0) (set dr (umod dr sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | 0x0 | 0xd | 0x6 |
(sequence () (set pc (and (reg h-cr 6) -4)) (set (reg h-cr 6) (reg h-cr 14)) (set (reg h-psw) (reg h-bpsw)) (set (reg h-bpsw) (reg h-bbpsw)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x5 | 0x0 | 0xe | 0x4 |
(set (reg h-accums 0) (add (sra (reg h-accums 1) 16) (reg h-accums 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-uimm16 |
0x8 | dr | 0x6 | sr | 0x0 |
(set dr (if WI condbit (if WI (lt sr 0) 2147483647 2147483648) sr))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-uimm16 |
0x8 | dr | 0x6 | sr | 0x300 |
(set dr (cond WI ((ge sr 127) 127) ((le sr -128) -128) (else . sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-uimm16 |
0x8 | dr | 0x6 | sr | 0x200 |
(set dr (cond WI ((ge sr 32767) 32767) ((le sr -32768) -32768) (else . sr)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x7 | 0x4 | 0x0 | 0x1 |
(skip (zext INT condbit))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-hi16 |
0xd | dr | 0xc | 0x0 | hi16 |
(set dr (sll WI hi16 16))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
f-op1 | f-r1 | f-uimm8 |
0x7 | 0x1 | uimm8 |
(set USI (reg h-cr 0) uimm8)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | dr | 0x4 | sr |
(set dr (sll dr (and sr 31)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0xc | sr | simm16 |
(set dr (sll sr (and WI simm16 31)))
0 1 2 3 | 4 5 6 7 | 8 9 10 | 11 12 13 14 15 |
f-op1 | f-r1 | f-shift-op2 | f-uimm5 |
0x5 | dr | 0x2 | uimm5 |
(set dr (sll dr uimm5))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x7 | 0x5 | 0x0 | 0x1 |
(skip (zext INT (not condbit)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | dr | 0x2 | sr |
(set dr (sra dr (and sr 31)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0xa | sr | simm16 |
(set dr (sra sr (and WI simm16 31)))
0 1 2 3 | 4 5 6 7 | 8 9 10 | 11 12 13 14 15 |
f-op1 | f-r1 | f-shift-op2 | f-uimm5 |
0x5 | dr | 0x1 | uimm5 |
(set dr (sra dr uimm5))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x1 | dr | 0x0 | sr |
(set dr (srl dr (and sr 31)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0x9 | dr | 0x8 | sr | simm16 |
(set dr (srl sr (and WI simm16 31)))
0 1 2 3 | 4 5 6 7 | 8 9 10 | 11 12 13 14 15 |
f-op1 | f-r1 | f-shift-op2 | f-uimm5 |
0x5 | dr | 0x0 | uimm5 |
(set dr (srl dr uimm5))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | src1 | 0x4 | src2 |
(set WI (mem WI src2) src1)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0xa | src1 | 0x4 | src2 | slo16 |
(set WI (mem WI (add src2 slo16)) src1)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | src1 | 0x7 | src2 |
(sequence ((WI new-src2)) (set new-src2 (sub src2 4)) (set (mem WI new-src2) src1) (set src2 new-src2))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | src1 | 0x6 | src2 |
(sequence ((WI new-src2)) (set new-src2 (add WI src2 4)) (set (mem WI new-src2) src1) (set src2 new-src2))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | src1 | 0x0 | src2 |
(set QI (mem QI src2) src1)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0xa | src1 | 0x0 | src2 | slo16 |
(set QI (mem QI (add src2 slo16)) src1)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | src1 | 0x1 | src2 |
(sequence ((QI new-src2)) (set (mem QI new-src2) src1) (set new-src2 (add src2 1)) (set src2 new-src2))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | src1 | 0x2 | src2 |
(set HI (mem HI src2) src1)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-simm16 |
0xa | src1 | 0x2 | src2 | slo16 |
(set HI (mem HI (add src2 slo16)) src1)
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | src1 | 0x3 | src2 |
(sequence ((HI new-src2)) (set (mem HI new-src2) src1) (set new-src2 (add src2 2)) (set src2 new-src2))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0x2 | sr |
(set dr (sub dr sr))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0x0 | sr |
(parallel () (set dr (sub dr sr)) (set condbit (sub-oflag dr sr 0)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0x1 | sr |
(parallel () (set dr (subc dr sr condbit)) (set condbit (sub-cflag dr sr condbit)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-uimm4 |
0x1 | 0x0 | 0xf | uimm4 |
(sequence () (set (reg h-cr 14) (reg h-cr 6)) (set (reg h-cr 6) (add pc 4)) (set (reg h-bbpsw) (reg h-bpsw)) (set (reg h-bpsw) (reg h-psw)) (set (reg h-psw) (and (reg h-psw) 128)) (set WI pc (c-call WI "m32r_trap" pc uimm4)))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x2 | src1 | 0x5 | src2 |
(sequence () (if (reg h-lock) (set (mem WI src2) src1)) (set (reg h-lock) 0))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
f-op1 | f-r1 | f-op2 | f-r2 |
0x0 | dr | 0xd | sr |
(set dr (xor dr sr))
0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-op1 | f-r1 | f-op2 | f-r2 | f-uimm16 |
0x8 | dr | 0xd | sr | uimm16 |
(set dr (xor sr uimm16))
((emit bc24 disp24))
((emit bc8 disp8))
((emit bcl24 disp24))
((emit bcl8 disp8))
((emit bl24 disp24))
((emit bl8 disp8))
((emit bnc24 disp24))
((emit bnc8 disp8))
((emit bncl24 disp24))
((emit bncl8 disp8))
((emit bra24 disp24))
((emit bra8 disp8))
((emit ld dr sr))
((emit ld-d dr sr slo16))
((emit ldb dr sr))
((emit ldb-d dr sr slo16))
((emit ldh dr sr))
((emit ldh-d dr sr slo16))
((emit ldi16 dr slo16))
((emit ldi8 dr simm8))
((emit ldub dr sr))
((emit ldub-d dr sr slo16))
((emit lduh dr sr))
((emit lduh-d dr sr slo16))
((emit ld-plus dr (sr 15)))
((emit st-minus src1 (src2 15)))
((emit rac-dsi accd (f-accs 0) (f-imm1 0)))
((emit rac-dsi accd accs (f-imm1 0)))
((emit rach-dsi accd (f-accs 0) (f-imm1 0)))
((emit rach-dsi accd accs (f-imm1 0)))
((emit st src1 src2))
((emit st-d src1 src2 slo16))
((emit stb src1 src2))
((emit stb-d src1 src2 slo16))
((emit sth src1 src2))
((emit sth-d src1 src2 slo16))
This documentation was machine generated from the cgen cpu description
files for this architecture.
http://sources.redhat.com/cgen/