ARM Instruction Documentation

Instructions

Instructions for each machine:

arm7tdmi - ARM 7TDMI core

MEM - Memory
ALU - ALU
BR - Branch
alphabetically

Individual instructions descriptions

add - add reg+reg

machines: base

syntax: add $rd,$rs,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op5 f-i f-addsub-op f-rn f-rs f-rd

0x3 0x0 0x0 rn rs rd

semantics:

(sequence
  ()
  (sequence
    ((SI result))
    (set result (addc rs rn 0))
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit (add-cflag rs rn 0))
    (set vbit (add-oflag rs rn 0)))
  (set rd (add rs rn)))

add-hd-hs - hi = hi + hi2

machines: base

syntax: add $hd,$hs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x0 0x1 0x1 hs hd

semantics:

(if (eq (index-of hd) 7)
    (set pc (add hd hs))
    (set hd (add hd hs)))

add-hd-rs - hi = hi + lo

machines: base

syntax: add $hd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x0 0x1 0x0 rs hd

semantics:

(if (eq (index-of hd) 7)
    (set pc (add hd rs))
    (set hd (add hd rs)))

add-rd-hs - lo = lo + hi

machines: base

syntax: add $rd,$hs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x0 0x0 0x1 hs rd

semantics:
```
(set rd (add rd hs))
```

add-sp - add offset to sp

machines: base

syntax: add sp,#$sword7

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op8 f-addoff-s f-sword7

0xb0 0x0 sword7

semantics:
```
(set sp (add sp sword7))
```

addi - add reg+imm

machines: base

syntax: add $rd,$rs,#$offset3

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op5 f-i f-addsub-op f-offset3 f-rs f-rd

0x3 0x1 0x0 offset3 rs rd

semantics:

(sequence
  ()
  (sequence
    ((SI result))
    (set result (addc rs offset3 0))
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit (add-cflag rs offset3 0))
    (set vbit (add-oflag rs offset3 0)))
  (set rd (add rs offset3)))

addi8 - add 8 bit immediate

machines: base

syntax: add ${bit10-rd},#$offset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-mcasi-op f-bit10-rd f-offset8

0x1 0x2 bit10-rd offset8

semantics:

(sequence
  ()
  (sequence
    ((SI result))
    (set result (addc bit10-rd offset8 0))
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit (add-cflag bit10-rd offset8 0))
    (set vbit (add-oflag bit10-rd offset8 0)))
  (set bit10-rd (add bit10-rd offset8)))

alu-adc - add with carry

machines: base

syntax: adc $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0x5 rs rd

semantics:

(sequence
  ((SI result))
  (set result (addc rd rs cbit))
  (sequence
    ((SI result))
    (set result (addc rd rs cbit))
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit (add-cflag rd rs cbit))
    (set vbit (add-oflag rd rs cbit)))
  (set rd result))

alu-and - and

machines: base

syntax: and $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0x0 rs rd

semantics:

(sequence
  ()
  (set rd (and rd rs))
  (sequence
    ()
    (set zbit (eq WI rd 0))
    (set nbit (lt WI rd 0))))

alu-asr - arithmetic shift right

machines: base

syntax: asr $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0x4 rs rd

semantics:

(sequence
  ((BI carry-out) (SI result))
  (set carry-out
       (c-call
         BI
         "compute_carry_out_regshift"
         rd
         (enum INT SHIFT-TYPE-asr)
         rs
         cbit))
  (set result (sra rd rs))
  (set rd result)
  (sequence
    ()
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit carry-out)))

alu-bic - bit clear

machines: base

syntax: bic $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0xe rs rd

semantics:

(sequence
  ()
  (set rd (and rd (inv rs)))
  (sequence
    ()
    (set zbit (eq WI rd 0))
    (set nbit (lt WI rd 0))))

alu-cmn - compare negative

machines: base

syntax: cmn $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0xb rs rd

semantics:

(sequence
  ((SI result))
  (set result (addc rd rs 0))
  (sequence
    ()
    (set zbit (eq WI result 0))
    (set nbit (lt WI result 0)))
  (set cbit (add-cflag rd rs 0))
  (set vbit (add-oflag rd rs 0)))

alu-cmp - compare

machines: base

syntax: cmp $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0xa rs rd

semantics:

(sequence
  ((SI result))
  (set result (subc rd rs 0))
  (sequence
    ()
    (set zbit (eq WI result 0))
    (set nbit (lt WI result 0)))
  (set cbit (not (sub-cflag rd rs 0)))
  (set vbit (sub-oflag rd rs 0)))

alu-eor - xor

machines: base

syntax: eor $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0x1 rs rd

semantics:

(sequence
  ()
  (set rd (xor rd rs))
  (sequence
    ()
    (set zbit (eq WI rd 0))
    (set nbit (lt WI rd 0))))

alu-lsl - logical shift left

machines: base

syntax: lsl $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0x2 rs rd

semantics:

(sequence
  ((BI carry-out) (SI result))
  (set carry-out
       (c-call
         BI
         "compute_carry_out_regshift"
         rd
         (enum INT SHIFT-TYPE-lsl)
         rs
         cbit))
  (set result (sll rd rs))
  (set rd result)
  (sequence
    ()
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit carry-out)))

alu-lsr - logical shift right

machines: base

syntax: lsr $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0x3 rs rd

semantics:

(sequence
  ((BI carry-out) (SI result))
  (set carry-out
       (c-call
         BI
         "compute_carry_out_regshift"
         rd
         (enum INT SHIFT-TYPE-lsr)
         rs
         cbit))
  (set result (srl rd rs))
  (set rd result)
  (sequence
    ()
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit carry-out)))

alu-mul - multiply

machines: base

syntax: mul $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0xd rs rd

semantics:

(sequence
  ()
  (set rd (mul rd rs))
  (sequence
    ()
    (set zbit (eq WI rd 0))
    (set nbit (lt WI rd 0))))

alu-mvn - invert

machines: base

syntax: mvn $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0xf rs rd

semantics:

(sequence
  ()
  (set rd (inv rs))
  (sequence
    ()
    (set zbit (eq WI rd 0))
    (set nbit (lt WI rd 0))))

alu-neg - negate

machines: base

syntax: neg $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0x9 rs rd

semantics:

(sequence
  ((SI result))
  (set result (neg rs))
  (sequence
    ((SI result))
    (set result (subc 0 rs 0))
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit (not (sub-cflag 0 rs 0)))
    (set vbit (sub-oflag 0 rs 0)))
  (set rd result))

alu-orr - or

machines: base

syntax: orr $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0xc rs rd

semantics:

(sequence
  ()
  (set rd (or rd rs))
  (sequence
    ()
    (set zbit (eq WI rd 0))
    (set nbit (lt WI rd 0))))

alu-ror - rotate right

machines: base

syntax: ror $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0x7 rs rd

semantics:

(sequence
  ((BI carry-out) (SI result))
  (set carry-out
       (c-call
         BI
         "compute_carry_out_regshift"
         rd
         (enum INT SHIFT-TYPE-ror)
         rs
         cbit))
  (set result (ror rd rs))
  (set rd result)
  (sequence
    ()
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit carry-out)))

alu-sbc - subtract with carry (borrow)

machines: base

syntax: sbc $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0x6 rs rd

semantics:

(sequence
  ((SI result))
  (set result (subc rd rs (not cbit)))
  (sequence
    ((SI result))
    (set result (subc rd rs (not cbit)))
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit (not (sub-cflag rd rs (not cbit))))
    (set vbit (sub-oflag rd rs (not cbit))))
  (set rd result))

alu-tst - test

machines: base

syntax: tst $rd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-alu-op f-rs f-rd

0x10 0x8 rs rd

semantics:

(sequence
  ((SI x))
  (set x (and rd rs))
  (sequence
    ()
    (set zbit (eq WI x 0))
    (set nbit (lt WI x 0))))

asr - arithmetic shift right

machines: base

syntax: asr $rd,$rs,#$offset5

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-shift-op f-offset5 f-rs f-rd

0x0 0x2 offset5 rs rd

semantics:

(sequence
  ((BI carry-out))
  (set carry-out
       (c-call
         BI
         "compute_carry_out_immshift"
         rs
         (enum INT SHIFT-TYPE-asr)
         offset5
         cbit))
  (set rd (sra rs offset5))
  (sequence
    ()
    (sequence
      ()
      (set zbit (eq WI rd 0))
      (set nbit (lt WI rd 0)))
    (set cbit carry-out)))

b - unconditional branch

machines: base

syntax: b $offset11

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op5 f-offset11

0x1c offset11

semantics:
```
(set pc offset11)
```

bcc - branch if cc (geu)

machines: base

syntax: bcc $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0x3 soffset8

semantics:
```
(if (not cbit) (set pc soffset8))
```

bcs - branch if cs (ltu)

machines: base

syntax: bcs $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0x2 soffset8

semantics:
```
(if cbit (set pc soffset8))
```

beq - branch if eq

machines: base

syntax: beq $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0x0 soffset8

semantics:
```
(if zbit (set pc soffset8))
```

bge - branch if ge

machines: base

syntax: bge $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0xa soffset8

semantics:

(if (not (xor nbit vbit)) (set pc soffset8))

bgt - branch if gt

machines: base

syntax: bgt $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0xc soffset8

semantics:

(if (not (or zbit (xor nbit vbit)))
    (set pc soffset8))

bhi - branch if hi (gtu)

machines: base

syntax: bhi $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0x8 soffset8

semantics:

(if (and cbit (not zbit)) (set pc soffset8))

bl-hi - branch link, high offset

machines: base

syntax: bl-hi ${lbwl-hi}

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-lbwl-h f-lbwl-hi

0xf 0x0 lbwl-hi

semantics:

(set lr (add (add pc 4) (sll lbwl-hi 12)))

bl-lo - branch link, low offset

machines: base

syntax: bl-lo ${lbwl-lo}

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-lbwl-h f-lbwl-lo

0xf 0x1 lbwl-lo

semantics:

(sequence
  ((WI cur-pc))
  (set cur-pc pc)
  (set pc (add lr (sll lbwl-lo 1)))
  (set lr (or (add cur-pc 2) 1)))

ble - branch if le

machines: base

syntax: ble $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0xd soffset8

semantics:

(if (or zbit (xor nbit vbit)) (set pc soffset8))

bls - branch if ls (leu)

machines: base

syntax: bls $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0x9 soffset8

semantics:

(if (or (not cbit) zbit) (set pc soffset8))

blt - branch if lt

machines: base

syntax: blt $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0xb soffset8

semantics:
```
(if (xor nbit vbit) (set pc soffset8))
```

bmi - branch if mi (negative)

machines: base

syntax: bmi $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0x4 soffset8

semantics:
```
(if nbit (set pc soffset8))
```

bne - branch if ne

machines: base

syntax: bne $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0x1 soffset8

semantics:
```
(if (not zbit) (set pc soffset8))
```

bpl - branch if pl (positive or zero)

machines: base

syntax: bpl $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0x5 soffset8

semantics:
```
(if (not nbit) (set pc soffset8))
```

bvc - branch if vc (overflow clear)

machines: base

syntax: bvc $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0x7 soffset8

semantics:
```
(if (not vbit) (set pc soffset8))
```

bvs - branch if vs (overflow set)

machines: base

syntax: bvs $soffset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-cond f-soffset8

0xd 0x6 soffset8

semantics:
```
(if vbit (set pc soffset8))
```

bx-hs - bx on hi reg

machines: base

syntax: bx $hs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x3 0x0 0x1 hs 0x0

semantics:

(sequence
  ()
  (set pc hs)
  (if (not (and hs 1)) (set (reg h-tbit) 0)))

bx-rs - bx on lo reg

machines: base

syntax: bx $rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x3 0x0 0x0 rs 0x0

semantics:

(sequence
  ()
  (set pc rs)
  (if (not (and rs 1)) (set (reg h-tbit) 0)))

cmp - cmp reg,imm

machines: base

syntax: cmp ${bit10-rd},#$offset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-mcasi-op f-bit10-rd f-offset8

0x1 0x1 bit10-rd offset8

semantics:

(sequence
  ((SI result))
  (set result (subc bit10-rd offset8 0))
  (sequence
    ()
    (set zbit (eq WI result 0))
    (set nbit (lt WI result 0)))
  (set cbit (not (sub-cflag bit10-rd offset8 0)))
  (set vbit (sub-oflag bit10-rd offset8 0)))

cmp-hd-hs - compare hi1,hi2

machines: base

syntax: cmp $hd,$hs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x1 0x1 0x1 hs hd

semantics:

(sequence
  ((SI result))
  (set result (subc hd hs 0))
  (sequence
    ()
    (set zbit (eq WI result 0))
    (set nbit (lt WI result 0)))
  (set cbit (not (sub-cflag hd hs 0)))
  (set vbit (sub-oflag hd hs 0)))

cmp-hd-rs - compare hi,lo

machines: base

syntax: cmp $hd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x1 0x1 0x0 rs hd

semantics:

(sequence
  ((SI result))
  (set result (subc hd rs 0))
  (sequence
    ()
    (set zbit (eq WI result 0))
    (set nbit (lt WI result 0)))
  (set cbit (not (sub-cflag hd rs 0)))
  (set vbit (sub-oflag hd rs 0)))

cmp-rd-hs - compare lo,hi

machines: base

syntax: cmp $rd,$hs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x1 0x0 0x1 hs rd

semantics:

(sequence
  ((SI result))
  (set result (subc rd hs 0))
  (sequence
    ()
    (set zbit (eq WI result 0))
    (set nbit (lt WI result 0)))
  (set cbit (not (sub-cflag rd hs 0)))
  (set vbit (sub-oflag rd hs 0)))

lda-pc - load address from pc

machines: base

syntax: add ${bit10-rd},pc,$word8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-sp f-bit10-rd f-word8

0xa 0x0 bit10-rd word8

semantics:

(set bit10-rd (add (and (add pc 4) -4) word8))

lda-sp - load address from sp

machines: base

syntax: add ${bit10-rd},sp,$word8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-sp f-bit10-rd f-word8

0xa 0x1 bit10-rd word8

semantics:
```
(set bit10-rd (add sp word8))
```

ldmia - load multiple

machines: base

syntax: ldmia $rb!,{$rlist}

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-bit10-rb f-rlist

0xc 0x1 bit10-rb rlist

semantics:

(sequence
  ()
  (if (and rlist (sll 1 0))
      (sequence
        ()
        (set (reg WI h-gr-t 0) (mem WI bit10-rb))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 1))
      (sequence
        ()
        (set (reg WI h-gr-t 1) (mem WI bit10-rb))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 2))
      (sequence
        ()
        (set (reg WI h-gr-t 2) (mem WI bit10-rb))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 3))
      (sequence
        ()
        (set (reg WI h-gr-t 3) (mem WI bit10-rb))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 4))
      (sequence
        ()
        (set (reg WI h-gr-t 4) (mem WI bit10-rb))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 5))
      (sequence
        ()
        (set (reg WI h-gr-t 5) (mem WI bit10-rb))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 6))
      (sequence
        ()
        (set (reg WI h-gr-t 6) (mem WI bit10-rb))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 7))
      (sequence
        ()
        (set (reg WI h-gr-t 7) (mem WI bit10-rb))
        (set bit10-rb (add bit10-rb 4)))))

ldr - load word

machines: base

syntax: ldr $rd,[$rb,$ro]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-b f-bit9 f-ro f-rb f-rd

0x5 0x1 0x0 0x0 ro rb rd

semantics:
```
(set rd (mem WI (add rb ro)))
```

ldr-imm - load word with immediate offset

machines: base

syntax: ldr $rd,[$rb,#${offset5-7}]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-b-imm f-l f-offset5-7 f-rb f-rd

0x3 0x0 0x1 offset5-7 rb rd

semantics:
```
(set rd (mem WI (add rb offset5-7)))
```

ldr-pc - pc relative load

machines: base

syntax: ldr ${bit10-rd},[pc,#$word8]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op5 f-bit10-rd f-word8

0x9 bit10-rd word8

semantics:

(set bit10-rd
     (mem WI (add (and (add pc 4) -4) word8)))

ldr-sprel - load word, sp-relative

machines: base

syntax: ldr ${bit10-rd},[sp,#$word8]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-bit10-rd f-word8

0x9 0x1 bit10-rd word8

semantics:
```
(set bit10-rd (mem WI (add sp word8)))
```

ldrb - load zero extended byte

machines: base

syntax: ldrb $rd,[$rb,$ro]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-b f-bit9 f-ro f-rb f-rd

0x5 0x1 0x1 0x0 ro rb rd

semantics:

(set rd (zext SI (mem QI (add rb ro))))

ldrb-imm - load zero extended byte with immediate offset

machines: base

syntax: ldrb $rd,[$rb,#$offset5]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-b-imm f-l f-offset5 f-rb f-rd

0x3 0x1 0x1 offset5 rb rd

semantics:

(set rd (zext SI (mem QI (add rb offset5))))

ldrh - load zero extended halfword

machines: base

syntax: ldrh $rd,[$rb,$ro]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-h f-s f-bit9 f-ro f-rb f-rd

0x5 0x1 0x0 0x1 ro rb rd

semantics:

(set rd (zext SI (mem HI (add rb ro))))

ldrh-imm - load zero extended halfword with immediate offset

machines: base

syntax: ldrh $rd,[$rb,#${offset5-6}]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-offset5-6 f-rb f-rd

0x8 0x1 offset5-6 rb rd

semantics:

(set rd (zext WI (mem HI (add rb offset5-6))))

ldsb - load sign extended byte

machines: base

syntax: ldsb $rd,[$rb,$ro]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-h f-s f-bit9 f-ro f-rb f-rd

0x5 0x0 0x1 0x1 ro rb rd

semantics:
```
(set rd (ext SI (mem QI (add rb ro))))
```

ldsh - load sign extended halfword

machines: base

syntax: ldsh $rd,[$rb,$ro]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-h f-s f-bit9 f-ro f-rb f-rd

0x5 0x1 0x1 0x1 ro rb rd

semantics:
```
(set rd (ext SI (mem HI (add rb ro))))
```

lsl - logical shift left

machines: base

syntax: lsl $rd,$rs,#$offset5

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-shift-op f-offset5 f-rs f-rd

0x0 0x0 offset5 rs rd

semantics:

(sequence
  ((BI carry-out))
  (set carry-out
       (c-call
         BI
         "compute_carry_out_immshift"
         rs
         (enum INT SHIFT-TYPE-lsl)
         offset5
         cbit))
  (set rd (sll rs offset5))
  (sequence
    ()
    (sequence
      ()
      (set zbit (eq WI rd 0))
      (set nbit (lt WI rd 0)))
    (set cbit carry-out)))

lsr - logical shift right

machines: base

syntax: lsr $rd,$rs,#$offset5

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-shift-op f-offset5 f-rs f-rd

0x0 0x1 offset5 rs rd

semantics:

(sequence
  ((BI carry-out))
  (set carry-out
       (c-call
         BI
         "compute_carry_out_immshift"
         rs
         (enum INT SHIFT-TYPE-lsr)
         offset5
         cbit))
  (set rd (srl rs offset5))
  (sequence
    ()
    (sequence
      ()
      (set zbit (eq WI rd 0))
      (set nbit (lt WI rd 0)))
    (set cbit carry-out)))

mov - move imm->reg

machines: base

syntax: mov ${bit10-rd},#$offset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-mcasi-op f-bit10-rd f-offset8

0x1 0x0 bit10-rd offset8

semantics:

(sequence
  ()
  (set bit10-rd offset8)
  (sequence
    ()
    (set zbit (eq WI bit10-rd 0))
    (set nbit (lt WI bit10-rd 0))))

mov-hd-hs - hi1 = hi2

machines: base

syntax: mov $hd,$hs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x2 0x1 0x1 hs hd

semantics:

(if (eq (index-of hd) 7) (set pc hs) (set hd hs))

mov-hd-rs - hi = lo

machines: base

syntax: mov $hd,$rs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x2 0x1 0x0 rs hd

semantics:

(if (eq (index-of hd) 7) (set pc rs) (set hd rs))

mov-rd-hs - lo = hi

machines: base

syntax: mov $rd,$hs

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op6 f-hireg-op f-h1 f-h2 f-rs f-rd

0x11 0x2 0x0 0x1 hs rd

semantics:
```
(set rd hs)
```

pop - pop registers

machines: base

syntax: pop {$rlist}

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-pushpop-op f-r f-rlist

0xb 0x1 0x2 0x0 rlist

semantics:

(sequence
  ()
  (if (and rlist (sll 1 0))
      (sequence
        ()
        (set (reg WI h-gr-t 0) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 1))
      (sequence
        ()
        (set (reg WI h-gr-t 1) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 2))
      (sequence
        ()
        (set (reg WI h-gr-t 2) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 3))
      (sequence
        ()
        (set (reg WI h-gr-t 3) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 4))
      (sequence
        ()
        (set (reg WI h-gr-t 4) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 5))
      (sequence
        ()
        (set (reg WI h-gr-t 5) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 6))
      (sequence
        ()
        (set (reg WI h-gr-t 6) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 7))
      (sequence
        ()
        (set (reg WI h-gr-t 7) (mem WI sp))
        (set sp (add sp 4)))))

pop-pc - pop registers and pc

machines: base

syntax: pop {${rlist-pc}}

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-pushpop-op f-r f-rlist

0xb 0x1 0x2 0x1 rlist

semantics:

(sequence
  ()
  (if (and rlist (sll 1 0))
      (sequence
        ()
        (set (reg WI h-gr-t 0) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 1))
      (sequence
        ()
        (set (reg WI h-gr-t 1) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 2))
      (sequence
        ()
        (set (reg WI h-gr-t 2) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 3))
      (sequence
        ()
        (set (reg WI h-gr-t 3) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 4))
      (sequence
        ()
        (set (reg WI h-gr-t 4) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 5))
      (sequence
        ()
        (set (reg WI h-gr-t 5) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 6))
      (sequence
        ()
        (set (reg WI h-gr-t 6) (mem WI sp))
        (set sp (add sp 4))))
  (if (and rlist (sll 1 7))
      (sequence
        ()
        (set (reg WI h-gr-t 7) (mem WI sp))
        (set sp (add sp 4))))
  (set pc (mem WI sp))
  (set sp (add sp 4)))

push - push registers

machines: base

syntax: push {$rlist}

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-pushpop-op f-r f-rlist

0xb 0x0 0x2 0x0 rlist

semantics:

(sequence
  ()
  (if (and rlist (sll 1 7))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 7))))
  (if (and rlist (sll 1 6))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 6))))
  (if (and rlist (sll 1 5))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 5))))
  (if (and rlist (sll 1 4))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 4))))
  (if (and rlist (sll 1 3))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 3))))
  (if (and rlist (sll 1 2))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 2))))
  (if (and rlist (sll 1 1))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 1))))
  (if (and rlist (sll 1 0))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 0)))))

push-lr - push registers and lr

machines: base

syntax: push {${rlist-lr}}

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-pushpop-op f-r f-rlist

0xb 0x0 0x2 0x1 rlist

semantics:

(sequence
  ()
  (set sp (sub sp 4))
  (set (mem WI sp) lr)
  (if (and rlist (sll 1 7))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 7))))
  (if (and rlist (sll 1 6))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 6))))
  (if (and rlist (sll 1 5))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 5))))
  (if (and rlist (sll 1 4))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 4))))
  (if (and rlist (sll 1 3))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 3))))
  (if (and rlist (sll 1 2))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 2))))
  (if (and rlist (sll 1 1))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 1))))
  (if (and rlist (sll 1 0))
      (sequence
        ()
        (set sp (sub sp 4))
        (set (mem WI sp) (reg WI h-gr-t 0)))))

stmia - store multiple

machines: base

syntax: stmia $rb!,{$rlist}

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-bit10-rb f-rlist

0xc 0x0 bit10-rb rlist

semantics:

(sequence
  ()
  (if (and rlist (sll 1 0))
      (sequence
        ()
        (set (mem WI bit10-rb) (reg WI h-gr-t 0))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 1))
      (sequence
        ()
        (set (mem WI bit10-rb) (reg WI h-gr-t 1))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 2))
      (sequence
        ()
        (set (mem WI bit10-rb) (reg WI h-gr-t 2))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 3))
      (sequence
        ()
        (set (mem WI bit10-rb) (reg WI h-gr-t 3))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 4))
      (sequence
        ()
        (set (mem WI bit10-rb) (reg WI h-gr-t 4))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 5))
      (sequence
        ()
        (set (mem WI bit10-rb) (reg WI h-gr-t 5))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 6))
      (sequence
        ()
        (set (mem WI bit10-rb) (reg WI h-gr-t 6))
        (set bit10-rb (add bit10-rb 4))))
  (if (and rlist (sll 1 7))
      (sequence
        ()
        (set (mem WI bit10-rb) (reg WI h-gr-t 7))
        (set bit10-rb (add bit10-rb 4)))))

str - store word

machines: base

syntax: str $rd,[$rb,$ro]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-b f-bit9 f-ro f-rb f-rd

0x5 0x0 0x0 0x0 ro rb rd

semantics:
```
(set (mem WI (add rb ro)) rd)
```

str-imm - store word with immediate offset

machines: base

syntax: str $rd,[$rb,#${offset5-7}]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-b-imm f-l f-offset5-7 f-rb f-rd

0x3 0x0 0x0 offset5-7 rb rd

semantics:
```
(set (mem WI (add rb offset5-7)) rd)
```

str-sprel - store word, sp-relative

machines: base

syntax: str ${bit10-rd},[sp,#$word8]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-bit10-rd f-word8

0x9 0x0 bit10-rd word8

semantics:
```
(set (mem WI (add sp word8)) bit10-rd)
```

strb - store byte

machines: base

syntax: strb $rd,[$rb,$ro]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-b f-bit9 f-ro f-rb f-rd

0x5 0x0 0x1 0x0 ro rb rd

semantics:
```
(set (mem QI (add rb ro)) rd)
```

strb-imm - store byte with immediate offset

machines: base

syntax: strb $rd,[$rb,#$offset5]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-b-imm f-l f-offset5 f-rb f-rd

0x3 0x1 0x0 offset5 rb rd

semantics:
```
(set (mem QI (add rb offset5)) rd)
```

strh - store halfword

machines: base

syntax: strh $rd,[$rb,$ro]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-h f-s f-bit9 f-ro f-rb f-rd

0x5 0x0 0x0 0x1 ro rb rd

semantics:
```
(set (mem HI (add rb ro)) rd)
```

strh-imm - store halfword with immediate offset

machines: base

syntax: strh $rd,[$rb,#${offset5-6}]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op4 f-l f-offset5-6 f-rb f-rd

0x8 0x0 offset5-6 rb rd

semantics:
```
(set (mem HI (add rb offset5-6)) rd)
```

sub - sub reg+reg

machines: base

syntax: sub $rd,$rs,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op5 f-i f-addsub-op f-rn f-rs f-rd

0x3 0x0 0x1 rn rs rd

semantics:

(sequence
  ()
  (sequence
    ((SI result))
    (set result (subc rs rn 0))
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit (not (sub-cflag rs rn 0)))
    (set vbit (sub-oflag rs rn 0)))
  (set rd (sub rs rn)))

sub-sp - subtract offset from sp

machines: base

syntax: add sp,#-$sword7

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op8 f-addoff-s f-sword7

0xb0 0x1 sword7

semantics:
```
(set sp (sub sp sword7))
```

subi - sub reg+imm

machines: base

syntax: sub $rd,$rs,#$offset3

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op5 f-i f-addsub-op f-offset3 f-rs f-rd

0x3 0x1 0x1 offset3 rs rd

semantics:

(sequence
  ()
  (sequence
    ((SI result))
    (set result (subc rs offset3 0))
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit (not (sub-cflag rs offset3 0)))
    (set vbit (sub-oflag rs offset3 0)))
  (set rd (sub rs offset3)))

subi8 - sub 8 bit immediate

machines: base

syntax: sub ${bit10-rd},#$offset8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op3 f-mcasi-op f-bit10-rd f-offset8

0x1 0x3 bit10-rd offset8

semantics:

(sequence
  ()
  (sequence
    ((SI result))
    (set result (subc bit10-rd offset8 0))
    (sequence
      ()
      (set zbit (eq WI result 0))
      (set nbit (lt WI result 0)))
    (set cbit (not (sub-cflag bit10-rd offset8 0)))
    (set vbit (sub-oflag bit10-rd offset8 0)))
  (set bit10-rd (sub bit10-rd offset8)))

swi - software interrupt

machines: base

syntax: swi $value8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-op8 f-value8

0xdf value8

semantics:

(set pc (c-call WI "thumb_swi" pc value8))

Macro Instructions

Macro instructions for each machine:

arm7tdmi - ARM 7TDMI core

arm7tdmi - ARM 7TDMI core

Individual macro-instructions descriptions

This documentation was machine generated from the cgen cpu description files for this architecture.
http://sources.redhat.com/cgen/

15 14 13 12 11	10	9	8 7 6	5 4 3	2 1 0
f-op5	f-i	f-addsub-op	f-rn	f-rs	f-rd
0x3	0x0	0x0	rn	rs	rd

15 14 13 12 11 10	9 8	7	6	5 4 3	2 1 0
f-op6	f-hireg-op	f-h1	f-h2	f-rs	f-rd
0x11	0x0	0x1	0x1	hs	hd

15 14 13 12 11 10 9 8	7	6 5 4 3 2 1 0
f-op8	f-addoff-s	f-sword7
0xb0	0x0	sword7

15 14 13	12 11	10 9 8	7 6 5 4 3 2 1 0
f-op3	f-mcasi-op	f-bit10-rd	f-offset8
0x1	0x2	bit10-rd	offset8

15 14 13 12 11 10	9 8 7 6	5 4 3	2 1 0
f-op6	f-alu-op	f-rs	f-rd
0x10	0x5	rs	rd

15 14 13	12 11	10 9 8 7 6	5 4 3	2 1 0
f-op3	f-shift-op	f-offset5	f-rs	f-rd
0x0	0x2	offset5	rs	rd

15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
f-op5	f-offset11
0x1c	offset11

15 14 13 12	11 10 9 8	7 6 5 4 3 2 1 0
f-op4	f-cond	f-soffset8
0xd	0x3	soffset8

15 14 13 12	11	10 9	8	7 6 5 4 3 2 1 0
f-op4	f-l	f-pushpop-op	f-r	f-rlist
0xb	0x1	0x2	0x0	rlist

15 14 13 12	11	10 9 8 7 6 5 4 3 2 1 0
f-op4	f-lbwl-h	f-lbwl-hi
0xf	0x0	lbwl-hi

15 14 13 12	11	10 9 8 7 6 5 4 3 2 1 0
f-op4	f-lbwl-h	f-lbwl-lo
0xf	0x1	lbwl-lo

Instructions

arm7tdmi MEM - Memory

arm7tdmi ALU - ALU

arm7tdmi BR - Branch

arm7tdmi arm7tdmi - ARM 7TDMI core

Individual instructions descriptions

add - add reg+reg

add-hd-hs - hi = hi + hi2

add-hd-rs - hi = hi + lo

add-rd-hs - lo = lo + hi

add-sp - add offset to sp

addi - add reg+imm

addi8 - add 8 bit immediate

alu-adc - add with carry

alu-and - and

alu-asr - arithmetic shift right

alu-bic - bit clear

alu-cmn - compare negative

alu-cmp - compare

alu-eor - xor

alu-lsl - logical shift left

alu-lsr - logical shift right

alu-mul - multiply

alu-mvn - invert

alu-neg - negate

alu-orr - or

alu-ror - rotate right

alu-sbc - subtract with carry (borrow)

alu-tst - test

asr - arithmetic shift right

b - unconditional branch

bcc - branch if cc (geu)

bcs - branch if cs (ltu)

beq - branch if eq

bge - branch if ge

bgt - branch if gt

bhi - branch if hi (gtu)

bl-hi - branch link, high offset

bl-lo - branch link, low offset

ble - branch if le

bls - branch if ls (leu)

blt - branch if lt

bmi - branch if mi (negative)

bne - branch if ne

bpl - branch if pl (positive or zero)

bvc - branch if vc (overflow clear)

bvs - branch if vs (overflow set)

bx-hs - bx on hi reg

bx-rs - bx on lo reg

cmp - cmp reg,imm

cmp-hd-hs - compare hi1,hi2

cmp-hd-rs - compare hi,lo

cmp-rd-hs - compare lo,hi

lda-pc - load address from pc

lda-sp - load address from sp

ldmia - load multiple

ldr - load word

ldr-imm - load word with immediate offset

ldr-pc - pc relative load

ldr-sprel - load word, sp-relative

ldrb - load zero extended byte

ldrb-imm - load zero extended byte with immediate offset

ldrh - load zero extended halfword

ldrh-imm - load zero extended halfword with immediate offset

ldsb - load sign extended byte

ldsh - load sign extended halfword

lsl - logical shift left

lsr - logical shift right

mov - move imm->reg

mov-hd-hs - hi1 = hi2

mov-hd-rs - hi = lo

mov-rd-hs - lo = hi

pop - pop registers

pop-pc - pop registers and pc

push - push registers

push-lr - push registers and lr

stmia - store multiple

str - store word

str-imm - store word with immediate offset

str-sprel - store word, sp-relative