The following opcodes are implementation-specific instructions of the e300 core (according to: e300 Power Architecture Core Family Reference Manual, Rev. 3): rfci, mfpmr, mtpmr. They are unrecognized opcodes for the assembler (GNU assembler (GNU Binutils) 2.18) if invoked with the -me300 option.
This should fix it: diff -u opcodes/ppc-opc.c* --- opcodes/ppc-opc.c 2008-08-14 09:32:22.000000000 +0200 +++ opcodes/ppc-opc.c.new 2008-08-14 09:32:18.000000000 +0200 @@ -3081,7 +3081,7 @@ {"rfdi", XL(19,39), 0xffffffff, E500MC, {0}}, {"rfi", XL(19,50), 0xffffffff, COM, {0}}, -{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE, {0}}, +{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, {0}}, {"rfsvc", XL(19,82), 0xffffffff, POWER, {0}}, @@ -3790,7 +3790,7 @@ {"div", XO(31,331,0,0), XO_MASK, M601, {RT, RA, RB}}, {"div.", XO(31,331,0,1), XO_MASK, M601, {RT, RA, RB}}, -{"mfpmr", X(31,334), X_MASK, PPCPMR, {RT, PMR}}, +{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, {RT, PMR}}, {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, {RT}}, {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, {RT}}, @@ -4094,7 +4094,7 @@ {"divwu", XO(31,459,0,0), XO_MASK, PPC, {RT, RA, RB}}, {"divwu.", XO(31,459,0,1), XO_MASK, PPC, {RT, RA, RB}}, -{"mtpmr", X(31,462), X_MASK, PPCPMR, {PMR, RS}}, +{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, {PMR, RS}}, {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, {RS}}, {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, {RS}},
Patch applied.