Bug 16017 - LD creates invalid PLT instructions on CORTEX-M3
Summary: LD creates invalid PLT instructions on CORTEX-M3
Status: RESOLVED FIXED
Alias: None
Product: binutils
Classification: Unclassified
Component: ld (show other bugs)
Version: 2.23
: P2 normal
Target Milestone: 2.34
Assignee: Tamar Christina
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2013-10-08 13:07 UTC by Markus Mayer
Modified: 2020-04-08 17:58 UTC (History)
5 users (show)

See Also:
Host:
Target:
Build:
Last reconfirmed:


Attachments
Patch for thumb plt entries (1.06 KB, patch)
2013-11-19 15:03 UTC, Markus Mayer
Details | Diff
[Rev2] Patch for thumb plt entries (2.03 KB, patch)
2013-11-22 09:31 UTC, Markus Mayer
Details | Diff
3rd version of patch (2.51 KB, patch)
2013-12-05 12:25 UTC, Nick Clifton
Details | Diff
v4 of patch, now with added mapping symbols (2.71 KB, patch)
2014-02-14 10:52 UTC, Nick Clifton
Details | Diff
Fix typo. Extend supported GOT offsets to 32-bits (2.71 KB, patch)
2014-02-14 14:42 UTC, Nick Clifton
Details | Diff
Fix another typo; remove assert (2.69 KB, patch)
2014-02-14 15:24 UTC, Nick Clifton
Details | Diff

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Description Markus Mayer 2013-10-08 13:07:30 UTC
When compiling a shared library for cortex-M3, ld creates ARM instructions for jumping to the plt and the plt itself. But the cortex only supports thumb instructions, which results in a runtime error.


Test case:
compile test.c with
arm-none-eabi-gcc -fPIC -nostartfiles -nostdlib -mcpu=cortex-m3 -mthumb -shared -o libtest.so test.c

test.c:
int foo();

int bar()
{

return foo();
}


Result:
Disassembly of section .plt:

00000238 <.plt>:
 238:   e52de004        push    {lr}            ; (str lr, [sp, #-4]!)
 23c:   e59fe004        ldr     lr, [pc, #4]    ; 248 <bar-0x10>
 240:   e08fe00e        add     lr, pc, lr
 244:   e5bef008        ldr     pc, [lr, #8]!
 248:   00008098        muleq   r0, r8, r0
 24c:   e28fc600        add     ip, pc, #0, 12
 250:   e28cca08        add     ip, ip, #8, 20  ; 0x8000
 254:   e5bcf098        ldr     pc, [ip, #152]! ; 0x98

Disassembly of section .text:

00000258 <bar>:
 258:   b580            push    {r7, lr}
 25a:   af00            add     r7, sp, #0
 25c:   f7ff eff6       blx     24c <bar-0xc>
 260:   4603            mov     r3, r0
 262:   4618            mov     r0, r3
 264:   bd80            pop     {r7, pc}
 266:   bf00            nop

24c, 250, 254 as well as 25c are ARM instructions and therefore invalid on cortex-m3 cores.


Possible related bugs:
bz#13320: Similar issue on gold
bz#13867: maybe related
bz#15628: similar issue in cortex-m4
Comment 1 Sourceware Commits 2013-11-14 15:42:22 UTC
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "gdb and binutils".

The branch, master has been updated
       via  57460bcf82df9e5e335be84ecc9bdef33dddc934 (commit)
      from  c7e8af9b3bc0881c59c999d7b78348d359383efe (commit)

Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=57460bcf82df9e5e335be84ecc9bdef33dddc934

commit 57460bcf82df9e5e335be84ecc9bdef33dddc934
Author: Nick Clifton <nickc@redhat.com>
Date:   Thu Nov 14 15:39:51 2013 +0000

    	PR ld/16017
    	* elf32-arm.c (elf32_arm_populate_plt_entry): Return a boolean
    	value, TRUE for success, FALSE for failure.
    	Fail if attempting to create a PLT entry for a thumb only target.
    	(elf32_arm_final_link_relocate): Check result of calling
    	elf32_arm_populate_plt_entry.
    	(elf32_arm_finish_dynamic_symbol): Likewise.

-----------------------------------------------------------------------

Summary of changes:
 bfd/ChangeLog   |   10 ++++++++++
 bfd/elf32-arm.c |   31 ++++++++++++++++++++++++-------
 2 files changed, 34 insertions(+), 7 deletions(-)
Comment 2 Nick Clifton 2013-11-14 15:43:45 UTC
Hi Markus,

  I do not have a solution for this problem, but I have checked in a patch to make the linker fail, with a suitable error message if an attempt is made to generate a PLT entry for a thumb-only processor.

Cheers
  Nick
Comment 3 Markus Mayer 2013-11-18 07:58:19 UTC
Hi Nick,

thanks for your reply. I have tried to fix it myself, but I am not familiar enough with the code base.

Is there anything I can do to help with this issue? e.g. providing assembler code for plt entries.
Comment 4 Nick Clifton 2013-11-18 12:22:32 UTC
Hi Markus,

> Is there anything I can do to help with this issue? e.g. providing assembler
> code for plt entries.

Yes please - that would help a lot.

Cheers
   Nick
Comment 5 Markus Mayer 2013-11-19 12:01:47 UTC
As I don't know what limitations exists for PLT entries I will provide different solutions.

Base assumptions:
- The IP register must contain the (absolute)address of the GOT entry (I think it is needed for lazy binding)

- If any register (except the IP register) is modified during the PLT execution, its state must be restored before the end of the PLT

- All PLT entries must have equal sizes


Solution 1:
1: b401            push    {r0}
2: f8df 0010       ldr.w   r0, [pc, #16]   ; load GOT index
3: f8df c010       ldr.w   ip, [pc, #16]   ; load (relative) GOT address
4: 4484            add     ip, r0
5: 44fc            add     ip, pc
6: bc01            pop     {r0}
7: f8dc f000       ldr.w   pc, [ip]
8: 00000000        ; GOT index
9: 00000000        ; GOT address relative to instruction in line 5

Pros: capable to handle arbitrary large GOT indexes as well as arbitrary offsets of the GOT
Cons: 28 Bytes per entry, 3 Load Instructions

Solution 2:
1: f8df c008       ldr.w   ip, [pc, #8]    ; load (relative)GOT entry address
2: 44fc            add     ip, pc
3: f8dc f000       ldr.w   pc, [ip]
4: 0000            ; padding to make the address aligned
5: 00000000        ; (GOT + GOT index) relative to instruction in line 2

Pros: only 16 Bytes per entry
Cons: still 2 load instructions, GOT and GOT index must be combined (is this possible?)

Solution 3:
1: f04f 0c00       mov.w   ip, #0
2: ea4f 3c0c       mov.w   ip, ip, lsl #12
3: f20f 0c00       addw    ip, pc, #0
4: f8dc f000       ldr.w   pc, [ip]

The GOT entry address is encoded in line 1 and line 3.
Pro: 16 Bytes per entry, only one load instruction
Con: only offsets up to 24 Bit are possible. (Note this limitation also exists for the current arm PLT)

I favour solution 3. I will provide code the generate a thumb plt later the day.
Comment 6 Markus Mayer 2013-11-19 15:03:48 UTC
Created attachment 7285 [details]
Patch for thumb plt entries
Comment 7 Markus Mayer 2013-11-19 15:13:42 UTC
I have attached a patch to create thumb plt entries. 

The patch has some issues:
- The plt entries are using tumb-2 instructions. When on an thumb only thumb-1 device, an error should be emitted.

- The plt0_entry for thumb-only is not converted yet. I will take care of it the next couple of days

- The size of a plt entry is set the thumb-entry size (which breaks normal arm linking). The plt size must be set according to whether we are on thumb-only, or not. I have tried using 'using_thumb_only', but it seams like 'abfd' is not fully initialized inside 'elf32_arm_link_hash_table_create' to work with 'using_thumb_only'.


Any help and feedback is welcome
Comment 8 Nick Clifton 2013-11-21 12:26:50 UTC
Hi Markus,

> The size of a plt entry is set the thumb-entry size (which breaks
>  normal arm linking).

Have you tried setting the entry size in
elf32_arm_create_dynamic_sections() ?


> The plt entries are using tumb-2 instructions. When on an thumb only
> thumb-1 device, an error should be emitted.

You can use "! using_thumb2()" for this.


The patch itself looks good so far...

Cheers
  Nick
Comment 9 Markus Mayer 2013-11-22 09:31:58 UTC
Created attachment 7291 [details]
[Rev2] Patch for thumb plt entries
Comment 10 Markus Mayer 2013-11-22 09:52:11 UTC
Hi Nick,

I have attached a new version of my previous patch.
Changes:
- convert pl0 to thumb
- Show error when using thumb-1 thumb-only targets
- Rename 'elf32_thumb_plt_entry' to 'elf32_thumb2_plt_entry'
- Set 'plt_entry_size' inside 'elf32_arm_create_dynamic_sections'
- Move 'using_thumb_only' and 'using_thumb2' upwards, to make it available inside 'elf32_arm_create_dynamic_sections'

Open issues:
- 'plt_entry_size' is still set incorrectly. 'using_thumb_only' return false inside 'elf32_arm_create_dynamic_sections'

- When calling the plt entry from the .text segment a 'BLX <immediate>' instruction is used. This instruction is not available in thumb mode. 'BL <immediate>' must be used here.

Can you help me out with these issues?


Regards
 Markus
Comment 11 Nick Clifton 2013-12-05 12:25:14 UTC
Created attachment 7314 [details]
3rd version of patch

Hi Markus,

   [Sorry for the delay in responding - I have been sidetracked by other tasks].

  Re: Detecting thumb_only inside create_dynamic_sections().  You are right - the normal function does not work.  This is because at the time that create_dynamic_sections is called the attributes have not been copied from the input bfd to the output bfd.  But... the attributes are still present in the input bfd, so you can test those.

  Re: Not converting BL into BLX - these was some code in final_link_relocate that assumed that PLT entries would always be in ARM mode, and so a BLX would always be needed.

  I have uploaded a revised version of your v2 patch with fixes for both of these problems.  Please try it out and let me know if it works for you.

Cheers
  Nick
Comment 12 Markus Mayer 2013-12-06 12:28:27 UTC
Hi Nick,

I've applied your patch and check the disassembly of a create test library. As far as I can tell it looks correct.

I haven't tested it on a real system, because my thumb-only system isn't available till late January.

If there are any problems left, it's like an error in the plt-code (which I can fix myself).

I will report my hardware test results as soon as there are available.


Regards
  Markus
Comment 13 Sourceware Commits 2013-12-13 16:52:49 UTC
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "gdb and binutils".

The annotated tag, hjl/linux/release/2.24.51.0.2 has been created
        at  bc64dc5b95aa848d7274e4648d667b9b1065d88c (tag)
   tagging  bbd7f545f1639be4573ba06ed688b8db670d4597 (commit)
  replaces  hjl/linux/release/2.24.51.0.1
 tagged by  H.J. Lu
        on  Fri Dec 13 08:44:03 2013 -0800

- Log -----------------------------------------------------------------
Linux binutils 2.24.51.0.2

Alan Modra (47):
      daily update
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Andreas Arnez (3):
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Andrew Burgess (6):
      Mark entirely optimized out value as non-lazy.
      Tighten regexp in gdb.base/setshow.exp
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      Print entirely unavailable struct/union values as a single <unavailable>.
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Anthony Green (1):
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      Fix assert failure with --emit-relocs and .eh_frame sections.
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      2013-11-11  Catherine Moore  <clm@codesourcery.com>
      Fix ChangeLog entries from earlier commit.
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      Small fix (first word of sentence to start with capital letter)
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      Replace "info-ada-exceptions" by "ada-exceptions" in -list-features
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      Fix DW_OP_GNU_regval_type with FP registers
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      Rename "read_reg" into "read_addr_from_reg" in struct dwarf_expr_context_funcs
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      Remove "ada-exceptions" from -list-features output.
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      crash evaluating bogus exception condition expression (sparc-solaris)
      Ada: Reserved word "all" should not need to be spelled in lowercase.
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      nameless LOAD_DLL_DEBUG_EVENT causes ntdll.dll to be missing
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      2013-11-07  Jose E. Marchesi  <jose.marchesi@oracle.com>
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Keith Seitz (4):
      Fix regressions caused by const-ify linespec patch:
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      PR c++/14819:  Explicit class:: inside class scope does not work

Keven Boell (1):
      testsuite: introduce index in varobj child eval.

Kyrylo Tkachov (1):
      [ld/testsuite/]

Luis Machado (2):
      * lib/mi-support.exp (mi_gdb_test): Expect different formats
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Maciej W. Rozycki (1):
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Michael Zolotukhin (1):
      Reorder invalid default mask check

Mike Frysinger (3):
      gdb: testsuite: fix ksh shebang to use sh
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Nick Clifton (8):
      * rescoff.c (write_coff_file): Use 64-bit alignment for resource
      PR ld/16082
      PR ld/16017
      * config/tc-aarch64.c (parse_sys_reg): Do not issue error messages
      * scripttempl/elf32msp430.sc (.data): Set the based on the next
      PR ld/16192
      * peXXigen.c (pe_print_resource_entries): New function: Displays
      * s390-mkopc.c (dumpTable): Provide a format string to printf so

Omair Javaid (1):
      testsuite/gdb.dwarf2: dw2-case-insensitive.exp: p fuNC_lang fails on arm

Pedro Alves (36):
      infrun.c:handle_inferior_event: Don't fall through in TARGET_WAITKIND_LOADED handling.
      infrun.c:handle_inferior_event: Move comment.
      infrun.c: Don't set ecs->random_signal for "catchpoint" events (eliminate ecs->random_signal).
      infrun.c:handle_inferior_event: Rework random signal checks.
      Eliminate enum bpstat_signal_value, simplify random signal checks further.
      infrun.c: Split handle_inferior_event further.
      infrun.c:handle_signal_stop: Move initial connection/attachment handling code earlier.
      Simplify dwarf2-frame.c:read_addr_from_reg.
      Make the maint.exp:'maint print objfiles' test less fragile.
      Add missing ChangeLog entry.
      Don't let two frames with the same id end up in the frame chain.
      Make use of the frame stash to detect wider stack cycles.
      Eliminate dwarf2_frame_cache recursion, don't unwind from the dwarf2 sniffer (move dwarf2_tailcall_sniffer_first elsewhere).
      Revert "Eliminate dwarf2_frame_cache recursion, don't unwind from the dwarf2 sniffer (move dwarf2_tailcall_sniffer_first elsewhere)."
      Revert "Make use of the frame stash to detect wider stack cycles."
      Revert "Don't let two frames with the same id end up in the frame chain."
      Eliminate dwarf2_frame_cache recursion, don't unwind from the dwarf2 sniffer (move dwarf2_tailcall_sniffer_first elsewhere).
      Don't let two frames with the same id end up in the frame chain.
      Make use of the frame stash to detect wider stack cycles.
      Rename gdb.dwarf2/dw2-bad-cfi.* to gdb.dwarf2/dw2-unspecified-ret-addr.*.
      Make "set debug frame 1" output print <not saved> instead of <optimized out>.
      Fix type of not saved registers.
      Fix PR 16152's ChangeLog entry.
      register: "optimized out" -> "not saved".
      get_prev_frame, UNWIND_NULL_ID -> UNWIND_OUTERMOST
      get_prev_frame, outer_frame_id and unwind->stop_reason checks are redundant.
      get_prev_frame, stop_reason != UNWIND_NO_REASON, add frame debug output.
      Plug target side conditions and commands leaks.
      UNWIND_NULL_ID is no longer used anywhere.  Update comments.
      Handle 'k' packet TARGET_CLOSE_ERROR gracefully.
      gnulib's sys/stat.h always defines S_IRGRP, S_IXGRP, S_IXOTH.
      Add new target_read_raw_memory function, and consolidate comments.
      New OPTIMIZED_OUT_ERROR error code.
      Fix "info frame" in the outermost frame.
      Eliminate UNSUPPORTED_ERROR.
      breakpoint.c:insert_bp_location: Constify local.

Phil Muldoon (4):
      2013-11-07  Phil Muldoon  <pmuldoon@redhat.com>
      2013-11-07  Phil Muldoon  <pmuldoon@redhat.com>
      2013-11-07  Phil Muldoon  <pmuldoon@redhat.com>
      2013-11-11  Phil Muldoon  <pmuldoon@redhat.com>

Pierre Muller (1):
      Fix completion for pascal language.

Richard Sandiford (1):
      binutils/testsuite/

Roland McGrath (4):
      Set CPU type in BFD backend for x86_64-nacl* and i?86-nacl* targets
      Fix references to __ehdr_start when it cannot be defined
      Fix *-nacl* target objcopy/strip of binary made with custom linker script
      Use $(INSTALL_PROGRAM_ENV) consistently.

Samuel Bronson (2):
      MAINTAINERS (Write After Approval): Add myself to the list.
      Resurrect gdb-add-index as a contrib script

Sanimir Agovic (1):
      test: test eval routines with EVAL_AVOID_SIDE_EFFECTS flag set

Senthil Kumar Selvaraj (1):
      * scripttempl/avr.sc: Set .data section's LMA to next available

Sergio Durigan Junior (2):
      Remove gdb_string.h from gdbarch.sh
      Sanitize access to gdbarch on the SDT probe API (and fix ARM bug)

Siva Chandra (1):
      2013-12-12  Siva Chandra Reddy  <sivachandra@google.com>

Steffen Sledz (1):
      gdb: fix cygwin check in configure script

Sterling Augustine (2):
      2013-11-22  Sterling Augustine  <saugustine@google.com>
      2013-11-22  Sterling Augustine  <saugustine@google.com>

Steve Ellcey (1):
      2013-11-25  Steve Ellcey  <sellcey@mips.com>

Tom Tromey (42):
      constify to_detach
      introduce common.m4
      remove link.h checks
      use gdb_string.h in m32c-tdep.c
      gdb configure updates
      fix a comment in configure.ac
      remove unused gdbserver configury
      fix "tkill" check
      fix multi-arch-exec for parallel mode
      off-by-one fix for py-linetable.c
      fix grammar oddity in the manual
      print summary from "make check"
      fix PR c++/16117
      link gdbreplay against gnulib
      change how list of modules is computed
      import strstr and strerror modules
      remove gdb_string.h
      don't check for string.h or strings.h
      import gnulib dirent module
      remove gdb_dirent.h
      don't check for stddef.h
      stdlib.h is universal too
      don't check for unistd.h
      sys/types.h cleanup
      import gnulib sys/stat.h module
      remove gdb_stat.h
      remove strerror module
      Detect infinite loop in value_fetch_lazy's lval_register handling.
      handle an unspecified return address column
      update comment in dw2-bad-cfi.S.
      revert patch from 2013-11-22
      add "dir" menu item for gdbserver
      add @kindex for catchpoints
      remove some sym_probe_fns methods
      make symtab::filename const
      make symtab::dirname const
      put the psymtab filename in the filename bcache
      fix a couple of FIXMEs
      pack partial_symtab for space
      remove unnecessary declaration
      remove objfile_to_front
      update free_objfile comment

Tristan Gingold (5):
      Fix version.dll binutils test on non native platforms
      Improve dump of xdata/pdata on x86_64.
      Fix crash on intelbad.
      Clear allocated target data.
      Add epilog unwind for x86_64 pe/coff

Walfred Tedeschi (9):
      Fix conditions in creating a bitfield.
      Add MPX registers XML files.
      Add MPX support for i386
      MPX for amd64
      Add MPX support to gdbserver.
      Add pretty-printer for MPX bnd registers.
      Add MPX registers tests.
      Fix PR16193 - gdbserver aborts.
      Documentation for MPX.

Will Newton (8):
      sim/arm: Prevent NULL pointer dereference in sim_create_inferior.
      sim/arm: Prevent crash when running sim with no binary.
      sim/ChangeLog: Correct bug number in previous commit.
      ld/ARM: Fix script-type testsuite failure.
      gdb/arm-tdep.c: Remove "Infinite loop detected" error message.
      bfd/elfnn-aarch64.c: Fix miscalculation of GOTPLT offset for ifunc syms.
      bfd/elfnn-aarch64.c: Handle static links with ifunc correctly.
      ld/testsuite/ld-aarch64: Fixup IFUNC tests to work on all targets

Yao Qi (36):
      Constify 'la_name' in struct language_defn
      New field 'la_natural_name' in struct language_defn
      Remove varobj_language_string, languages and varobj_languages
      Fix typo
      Remove 'whatever' in lib/mi-support.exp
      Fix format issues in lib/mi-support.exp
      Remove unnecessary '\'.
      Move changelog entry to the right ChangeLog
      Remove last_cache
      Don't update target_dcache if it is not initialized
      Move target-dcache out of target.c
      Don't stress 'remote' in "Data Caching" in doc
      Add REGISTRY for struct address_space.
      Associate target_dcache to address_space.
      set_address_space_data if dcache is NULL.
      s/see @pxref/@pxref in doc
      Doc 'dynamic' for command -var-list-children
      Use mi_create_floating_varobj
      Check has_more in mi_create_dynamic_varobj
      Update doc on displayhint in command -var-list-children
      Write "ON" and "OFF" in lower case in GDB doc.
      GDB perf test on single step
      Renaming in target-dcache.c
      set/show code-cache
      Use target_read_code in disassemble.
      GDB perf test on backtrace
      GDB perf test on disassemble
      Delegate to target_ops->beneath for TARGET_OBJECT_RAW_MEMORY
      Fix typo "checksm"
      Fix PR remote/15974
      Avoid "may be used uninitialized" warning
      Use gdb_produce_source
      Invalidate target cache before starting to handle event.
      Use target_read_code in skip_prologue (i386)
      Use target_read_code in skip_prologue (amd64)
      Fix a bug in matching notifications.

Yufeng Zhang (8):
      * elfxx-aarch64.c (_bfd_aarch64_elf_grok_prstatus): Fix hard-coded
      bfd/
      gas/
      Revert "Add support for AArch64 trace unit registers."
      gas/
      Add support for armv7ve to gas.
      Revert "Do not issue error messages when parsing a PSTATE register".
      gas/testsuite/

bviyer (2):
      Added Cilk runtime library (libcilkrts) into GCC.
      Disable libcilkrts when C++ is not used.

ccoutant (1):
      Fix demangler to handle conversion operators correctly.

gary (1):
      libiberty/ 2013-10-25 Gary Benson <gbenson@redhat.com>

gerald (3):
      Fix up ChangeLog entries (name, e-mail, formatting, otherwise).
      * testsuite/test-expandargv.c: Include unistd.h.
      * testsuite/test-demangle.c: Include unistd.h.

glisse (1):
      2013-10-29 Marc Glisse <marc.glisse@inria.fr>

jason (1):
      / * Makefile.tpl (STAGE1_CONFIGURE_FLAGS): Pass --disable-build-format-warnings. gcc/ * configure.ac (loose_warn): Add -Wno-format if --disable-build-format-warnings.

law (1):
      * Makefile.def (target_modules): Remove libmudflap (languages): Remove check-target-libmudflap). * Makefile.in: Rebuilt. * Makefile.tpl (check-target-libmudflap-c++): Remove. * configure.ac (target_libraries): Remove target-libmudflap. Remove checks which disabled libmudflap on some systems. * configure: Rebuilt. * libmudflap: Directory removed.

rsandifo (1):
      include/ * longlong.h: New file.

schwab (1):
      config/ * picflag.m4 (m68k-*-*): Use default PIC flag.

sterling (1):
      2013-10-22 Sterling Augustine <saugustine@google.com>

tschwinge (2):
      * Makefile.tpl: Fix typo. * Makefile.in: Regenerate.
      * Makefile.in: Regenerate.

uros (1):
      * cp-demangle.c (d_copy_templates): Cast result of malloc to (struct d_print_template *). (d_print_comp): Cast result of realloc to (struct d_saved scope *).

-----------------------------------------------------------------------
Comment 14 Meador Inge 2014-01-31 16:57:30 UTC
I have a need for these patches as well.  While testing them, we noticed that the current PLT stubs have a bug:

   0x0c00f240,		/* movw    ip, #0xNNNN    */
   0x3c0cea4f,		/* lsl     ip, #12        */
   0x0c00f20f,		/* addw    ip, pc, #0xNNN */
   0xf000f8dc,		/* ldr     pc, [ip]       */

The third instructions clobbers 'ip'.  Thus for non-zero 'ip' values this will not work.
Comment 15 Irfan Ahmad 2014-01-31 17:38:33 UTC
One problem in coming up with a compact PLT, in present case, is that PC is not allowed to be a source operand in ADD (and OR) instructions that take register parameters (e.g. - add ip, pc - is illegal). So an intermediate register is needed. I suggest the following variant:

1: b401            push    {r0}
2: f20f 0000       addw    r0, pc, #0
3: f240 0c00       movw    ip, #0x0000 ; Lower 16 bits of GOT entry offset from PC
4: f2c0 0c00       movt    ip, #0x0000 ; Upper 16 bits of GOT entry offset from PC
5: 4484            add     ip, r0
6: bc01            pop     {r0}
7: f8dc f000       ldr.w   pc, [ip]

This comes to 22 bytes but has the plus side that 32-bit offsets can be handled allowing GOT to be anywhere in the 32-bit address space.
Comment 16 Markus Mayer 2014-01-31 18:30:32 UTC
Will thinking about it, I came to the following conclusion (only line 2 differs). It safes 2 byte.

1: push    {r0}
2: mov     r0, pc
3: movw    ip, #0x0000 ; Lower 16 bits of GOT entry offset from PC
4: movt    ip, #0x0000 ; Upper 16 bits of GOT entry offset from PC
5: add     ip, r0
6: pop     {r0}
7: ldr.w   pc, [ip]
Comment 17 Irfan Ahmad 2014-01-31 18:40:45 UTC
I missed an && in the ARM reference manual, :(

add    ip, pc

Should be legal

addw   ip, pc, #0

is not.

So we can rework my suggestion to:

1: f240 0c00       movw    ip, #0x0000 ; Lower 16 bits of GOT entry offset
2: f2c0 0c00       movt    ip, #0x0000 ; Upper 16 bits of GOT entry offset
3: 44fc            add     ip, pc
4: f8dc f000       ldr.w   pc, [ip]

This will result in the same size as in the Solution 3 by Markus.
Comment 18 Meador Inge 2014-01-31 18:45:20 UTC
Right, my reading of the ARM manuals suggest that with 'ADD <Rdn>, <Rm>' (T2 encoding) that Rm can be PC. Only things like 'ADD PC, Rm' and 'ADD PC, PC' are unpredictable.

I came up with a similar encoding:

   0:	f240 0c00 	movw	ip, #0
   4:	f2c0 0c00 	movt	ip, #0
   8:	44fc      	add	ip, pc
   a:	f8dc f000 	ldr.w	pc, [ip]
   e:	bf00      	nop

We might need the nop to group things into a multiple of 4.
Comment 19 Nick Clifton 2014-02-14 10:52:24 UTC
Created attachment 7414 [details]
v4 of patch, now with added mapping symbols

Hi Guys,

  I have uploaded a revised version of the patch containing the fixed PLT entry code.  If someone can confirm that this works I will be happy to check it in.

  Note - this version of the patch also adds in setting the mapping symbols correctly so that the .plt section can be disassembled correctly.

Cheers
  Nick
Comment 20 Meador Inge 2014-02-14 14:26:20 UTC
Hi Nick,

Thanks for the update.  A few questions/observations:

1. I think the third mask on 'elf32_thumb2_plt_entry[1]' when applying
   the constants should be '0x08000000' instead of '0x08000800'.

2. Why do we limit the offset to 24 bits?  It seems the encoding allows
   for a full 32 bits, e.g. a fourth line that does:

     | ((got_displacement & 0xf0000000) >> 28)


   I understand why the 'elf32_arm_plt_entry' has this limitation.
Comment 21 Nick Clifton 2014-02-14 14:42:46 UTC
Created attachment 7415 [details]
Fix typo.  Extend supported GOT offsets to 32-bits

Hi Meadori,

  Ooops - you are right.  The mask was a typo, and the lack of full 32-bit GOT offset support was just plain laziness.  Please try out this revised version instead.

Cheers
  Nick
Comment 22 Meador Inge 2014-02-14 14:58:56 UTC
Hi Nick,

I just noticed that the mask for 'elf32_thumb2_plt_entry[0]' has the same typo, but the upper 8 needs to be removed instead.  I had to squint to see it :-)

Also, we should remove the 'BFD_ASSERT ((got_displacement & 0xf0000000) == 0)' assert now that 32-bit support is there.  Other than that, looks good to me!
Comment 23 Nick Clifton 2014-02-14 15:24:02 UTC
Created attachment 7416 [details]
Fix another typo; remove assert

Hi Meadori,

  Thanks again for checking the patch.  I have uploaded another version.  This time it will work and no-one will have to be nailed to anything.  (Sorry - old quote...)

Cheers
  Nick
Comment 24 Meador Inge 2014-02-14 16:10:53 UTC
Thanks Nick!  The last version looks good.  We will try some runtime testing on it.
Comment 25 Meador Inge 2014-03-03 20:28:37 UTC
Hi Nick,

The runtime testing we did with this patch worked for our use cases.  Thanks again.
Comment 26 Sourceware Commits 2014-03-04 15:27:50 UTC
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "gdb and binutils".

The branch, master has been updated
       via  eed94f8f8eddbd2268fc317508044bedc81a4e70 (commit)
      from  1a8a700e3a6fd88bcd5b3988a1f738da463f5b1b (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=eed94f8f8eddbd2268fc317508044bedc81a4e70

commit eed94f8f8eddbd2268fc317508044bedc81a4e70
Author: Nick Clifton <nickc@redhat.com>
Date:   Tue Mar 4 15:25:53 2014 +0000

    Install patch for PR ld/16017.  This adds support for generating PLT entries
    using Thumb2 instructions for those cores which do not support the ARM ISA.
    
    	* elf32-arm.c (elf32_thumb2_plt0_entry): New array.
    	(elf32_thumb2_plt_entry): New array.
    	(elf32_arm_create_dynamic_sections): Set PLT entry sizes when
    	using thumb2 based PLT.
    	(elf32_arm_populate_plt_entry): Handle generating Thumb2 based PLT
    	entries.
    	(elf32_arm_final_link_relocate): Do not bias jumps to Thumb based
    	PLT entries.
    	(elf32_arm_finish_dynamic_sections): Handle creation of Thumb2
    	based PLT 0-entry.
    	(elf32_arm_output_plt_map_1): Handle creation of local symbols for
    	Thumb2 based PLT 0-entry.
    	(elf32_arm_output_arch_local_syms): Handle creation of local
    	symbols for Thumb2 based PLT entries.

-----------------------------------------------------------------------

Summary of changes:
 bfd/ChangeLog   |   18 +++++
 bfd/elf32-arm.c |  188 ++++++++++++++++++++++++++++++++++++++++++------------
 2 files changed, 164 insertions(+), 42 deletions(-)
Comment 27 Nick Clifton 2014-03-04 15:28:48 UTC
I have checked in the final version of the patch.
Comment 28 Tamar Christina 2020-03-26 18:00:14 UTC
Looks like the initial GOT entries pointing to PLT0 are missing Thumb bit being set. The current version will transition out of Thumb mode and crash.
Comment 29 Sourceware Commits 2020-04-01 09:53:52 UTC
The master branch has been updated by Tamar Christina <tnfchris@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=a7618269b727da9cf56727c22cb538ff5f0e4d25

commit a7618269b727da9cf56727c22cb538ff5f0e4d25
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Wed Apr 1 10:47:18 2020 +0100

    Arm: Fix LSB of GOT for Thumb2 only PLT.
    
    When you have a Thumb only PLT then the address in the GOT for PLT0 needs to
    have the Thumb bit set since the instruction used in PLTn to get there is
    `ldr.w  pc` which is an inter-working instruction:
    
    the PLT sequence in question is
    
    00000120 <foo@plt>:
     120:   f240 0c98       movw    ip, #152        ; 0x98
     124:   f2c0 0c01       movt    ip, #1
     128:   44fc            add     ip, pc
     12a:   f8dc f000       ldr.w   pc, [ip]
     12e:   e7fc            b.n     12a <foo@plt+0xa>
    
    Disassembly of section .text:
    
    00000130 <bar>:
     130:   b580            push    {r7, lr}
     132:   af00            add     r7, sp, #0
     134:   f7ff fff4       bl      120 <foo@plt>
    
    and previously the linker would generate
    
    Hex dump of section '.got':
     ...
      0x000101b8 40010100 00000000 00000000 10010000 @...............
    
    Which would make it jump and transition out of thumb mode and crash since you
    only have thumb mode on such cores.
    
    Now it correctly generates
    
    Hex dump of section '.got':
     ...
      0x000101b8 40010100 00000000 00000000 11010000 @...............
    
    Thanks to Amol for testing patch and to rgujju for reporting it.
    
    bfd/ChangeLog:
    
            PR ld/16017
            * elf32-arm.c (elf32_arm_populate_plt_entry): Set LSB of the PLT0
            address in the GOT if in thumb only mode.
    
    ld/ChangeLog:
    
            PR ld/16017
            * testsuite/ld-arm/arm-elf.exp (thumb-plt-got): New.
            * testsuite/ld-arm/thumb-plt-got.d: New test.
Comment 30 Sourceware Commits 2020-04-01 17:56:25 UTC
The master branch has been updated by Tamar Christina <tnfchris@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3ce23ca1de4c769c4b7247f0724a10ef5fb24a11

commit 3ce23ca1de4c769c4b7247f0724a10ef5fb24a11
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Wed Apr 1 18:31:22 2020 +0100

    Arm: Skip Thumb2 PLT tests on NaCL.
    
    NaCL does not support dynamic linking and so these tests should be
    skipped under it.
    
    ld/ChangeLog:
    
            PR ld/16017
            * testsuite/ld-arm/arm-elf.exp (thumb-plt, thumb-plt-got): Skip for NaCL.
Comment 31 Sourceware Commits 2020-04-08 17:56:25 UTC
The binutils-2_34-branch branch has been updated by Tamar Christina <tnfchris@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=aaf3f0599a210699a76767c07a7d7f62d7633d71

commit aaf3f0599a210699a76767c07a7d7f62d7633d71
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Wed Apr 1 10:47:18 2020 +0100

    Arm: Fix LSB of GOT for Thumb2 only PLT.
    
    When you have a Thumb only PLT then the address in the GOT for PLT0 needs to
    have the Thumb bit set since the instruction used in PLTn to get there is
    `ldr.w  pc` which is an inter-working instruction:
    
    the PLT sequence in question is
    
    00000120 <foo@plt>:
     120:   f240 0c98       movw    ip, #152        ; 0x98
     124:   f2c0 0c01       movt    ip, #1
     128:   44fc            add     ip, pc
     12a:   f8dc f000       ldr.w   pc, [ip]
     12e:   e7fc            b.n     12a <foo@plt+0xa>
    
    Disassembly of section .text:
    
    00000130 <bar>:
     130:   b580            push    {r7, lr}
     132:   af00            add     r7, sp, #0
     134:   f7ff fff4       bl      120 <foo@plt>
    
    and previously the linker would generate
    
    Hex dump of section '.got':
     ...
      0x000101b8 40010100 00000000 00000000 10010000 @...............
    
    Which would make it jump and transition out of thumb mode and crash since you
    only have thumb mode on such cores.
    
    Now it correctly generates
    
    Hex dump of section '.got':
     ...
      0x000101b8 40010100 00000000 00000000 11010000 @...............
    
    Thanks to Amol for testing patch and to rgujju for reporting it.
    
    bfd/ChangeLog:
    
            PR ld/16017
            * elf32-arm.c (elf32_arm_populate_plt_entry): Set LSB of the PLT0
            address in the GOT if in thumb only mode.
    
    ld/ChangeLog:
    
            PR ld/16017
            * testsuite/ld-arm/arm-elf.exp (thumb-plt-got): New.
            * testsuite/ld-arm/thumb-plt-got.d: New test.
    
    (cherry picked from commit a7618269b727da9cf56727c22cb538ff5f0e4d25)
    (cherry picked from commit 3ce23ca1de4c769c4b7247f0724a10ef5fb24a11)
Comment 32 Tamar Christina 2020-04-08 17:58:18 UTC
fixed in master and 2.34