Created attachment 5939 [details]
example of ARM provided code that makes use of strexh strexb with same registers

In gas version 2.21.53, when compiling for the Cortex-M3 with -mcpu=cortex-m3 -march=armv7-m, the following instructions generate assembler errors:

strexh r0, r0, [r1]
strexb r0, r0, [r1]

The error messages are:
Error: registers may not be the same -- `strexh r0,r0,[r1]'
Error: registers may not be the same -- `strexb r0,r0,[r1]'

However, according to the ARM documentation of STREX for the Cortex M3 [0], only the word sized (32-bit) version of the instruction strex has the restriction that the three registers be unique:

for STREX, Rd must be different from both Rt and Rn

This problem shows up, for example, when trying to compile vendor provided peripheral libraries that make use of CMSIS.  In particular, the core_cm3.[ch] of CMSIS v1.3, and core_cmInstr.h of CMSIS v2.0 have all of these instructions.  Curiously, even strex r0, r0, [r1] shows up in CMSIS, even though this is explicitly restricted in [0].  So perhaps even some of the CMSIS code is breaking the specification of the ARM documentation, not sure.

[0] -- http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABFFBJB.html