[hjl@gnu-6 tmp]$ cat ilp32-6.s .globl _start _start: mov $_start,%rax mov _start,%rax [hjl@gnu-6 tmp]$ as --x32 -o ilp32-6.o ilp32-6.s [hjl@gnu-6 tmp]$ ld -m elf32_x86_64 -Ttext-segment 0x80000000 ilp32-6.o [hjl@gnu-6 tmp]$ objdump -dw a.out a.out: file format elf32-x86-64 Disassembly of section .text: 80000054 <_start>: 80000054: 48 c7 c0 54 00 00 80 mov $0xffffffff80000054,%rax 8000005b: 48 8b 04 25 54 00 00 80 mov 0xffffffff80000054,%rax [hjl@gnu-6 tmp]$ Linker should detect address overflow.
CVSROOT: /cvs/src Module name: src Changes by: hjl@sourceware.org 2011-08-01 23:04:24 Modified files: bfd : ChangeLog archures.c bfd-in2.h cpu-i386.c elf64-x86-64.c gas : ChangeLog gas/config : tc-i386.c tc-i386.h gas/testsuite : ChangeLog gas/testsuite/gas/i386/ilp32: ilp32.exp quad.d x86-64-pcrel.d x86-64-pcrel.s ld/testsuite : ChangeLog ld/testsuite/ld-x86-64: x86-64.exp opcodes : ChangeLog i386-dis.c Added files: ld/testsuite/ld-x86-64: ilp32-6.d ilp32-6.s ilp32-7.d ilp32-7.s ilp32-8.d ilp32-8.s ilp32-9.d ilp32-9.s Removed files: gas/testsuite/gas/i386/ilp32: inval.l inval.s Log message: Check R_X86_64_32 overflow and allow R_X86_64_64 for x32. bfd/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * archures.c (bfd_mach_i386_intel_syntax): New. (bfd_mach_i386_i8086): Updated. (bfd_mach_i386_i386): Likewise. (bfd_mach_x86_64): Likewise. (bfd_mach_x64_32): Likewise. (bfd_mach_i386_i386_intel_syntax): Likewise. (bfd_mach_x86_64_intel_syntax): Likewise. (bfd_mach_x64_32_intel_syntax): Likewise. (bfd_mach_l1om): Likewise. (bfd_mach_l1om_intel_syntax): Likewise. (bfd_mach_k1om): Likewise. (bfd_mach_k1om_intel_syntax): Likewise. * bfd-in2.h: Regenerated. * cpu-i386.c (bfd_i386_compatible): Check mach instead of bits_per_address. (bfd_x64_32_arch_intel_syntax): Set bits_per_address to 64. (bfd_x64_32_arch): Likewise. * elf64-x86-64.c: Include "libiberty.h". (x86_64_elf_howto_table): Append x32 R_X86_64_32. (elf_x86_64_rtype_to_howto): Support x32 R_X86_64_32. (elf_x86_64_reloc_type_lookup): Likewise. (elf_x86_64_reloc_name_lookup): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_check_relocs): Allow R_X86_64_64 relocations for x32. gas/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * config/tc-i386.c (handle_quad): Removed. (md_pseudo_table): Remove "quad". (tc_gen_reloc): Don't check BFD_RELOC_64 for disallow_64bit_reloc. (x86_dwarf2_addr_size): New. * config/tc-i386.h (x86_dwarf2_addr_size): New. (DWARF2_ADDR_SIZE): Likewise. gas/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * gas/i386/ilp32/ilp32.exp: Don't run inval. * gas/i386/ilp32/inval.l: Removed. * gas/i386/ilp32/inval.s: Likewise. * gas/i386/ilp32/quad.d: Expect R_X86_64_64 instead of R_X86_64_32. * gas/i386/ilp32/x86-64-pcrel.s: Add tests for movabs. * gas/i386/ilp32/x86-64-pcrel.d: Updated. ld/testsuite/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * ld-x86-64/ilp32-6.d: New. * ld-x86-64/ilp32-6.s: Likewise. * ld-x86-64/ilp32-7.d: Likewise. * ld-x86-64/ilp32-7.s: Likewise. * ld-x86-64/ilp32-8.d: Likewise. * ld-x86-64/ilp32-8.s: Likewise. * ld-x86-64/ilp32-9.d: Likewise. * ld-x86-64/ilp32-9.s: Likewise. * ld-x86-64/x86-64.exp: Run ilp32-6, ilp32-7, ilp32-8 and ilp32-9. opcodes/ 2011-08-01 H.J. Lu <hongjiu.lu@intel.com> PR ld/13048 * i386-dis.c (print_insn): Optimize info->mach check. Patches: http://sourceware.org/cgi-bin/cvsweb.cgi/src/bfd/ChangeLog.diff?cvsroot=src&r1=1.5439&r2=1.5440 http://sourceware.org/cgi-bin/cvsweb.cgi/src/bfd/archures.c.diff?cvsroot=src&r1=1.157&r2=1.158 http://sourceware.org/cgi-bin/cvsweb.cgi/src/bfd/bfd-in2.h.diff?cvsroot=src&r1=1.544&r2=1.545 http://sourceware.org/cgi-bin/cvsweb.cgi/src/bfd/cpu-i386.c.diff?cvsroot=src&r1=1.20&r2=1.21 http://sourceware.org/cgi-bin/cvsweb.cgi/src/bfd/elf64-x86-64.c.diff?cvsroot=src&r1=1.237&r2=1.238 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/ChangeLog.diff?cvsroot=src&r1=1.4556&r2=1.4557 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/config/tc-i386.c.diff?cvsroot=src&r1=1.477&r2=1.478 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/config/tc-i386.h.diff?cvsroot=src&r1=1.121&r2=1.122 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1935&r2=1.1936 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/i386/ilp32/ilp32.exp.diff?cvsroot=src&r1=1.5&r2=1.6 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/i386/ilp32/quad.d.diff?cvsroot=src&r1=1.2&r2=1.3 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/i386/ilp32/x86-64-pcrel.d.diff?cvsroot=src&r1=1.2&r2=1.3 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/i386/ilp32/x86-64-pcrel.s.diff?cvsroot=src&r1=1.1&r2=1.2 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/i386/ilp32/inval.l.diff?cvsroot=src&r1=1.3&r2=NONE http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/i386/ilp32/inval.s.diff?cvsroot=src&r1=1.3&r2=NONE http://sourceware.org/cgi-bin/cvsweb.cgi/src/ld/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1450&r2=1.1451 http://sourceware.org/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-x86-64/ilp32-6.d.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-x86-64/ilp32-6.s.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-x86-64/ilp32-7.d.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-x86-64/ilp32-7.s.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-x86-64/ilp32-8.d.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-x86-64/ilp32-8.s.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-x86-64/ilp32-9.d.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-x86-64/ilp32-9.s.diff?cvsroot=src&r1=NONE&r2=1.1 http://sourceware.org/cgi-bin/cvsweb.cgi/src/ld/testsuite/ld-x86-64/x86-64.exp.diff?cvsroot=src&r1=1.35&r2=1.36 http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1746&r2=1.1747 http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/i386-dis.c.diff?cvsroot=src&r1=1.263&r2=1.264
Fixed.