The annotation of ldrd instructions in Thumb during disassembly appears incomplete: the target label is not annotated, whereas for ldr, or for ldr or ldrd in ARM, the instruction is annotated with the target label in the disassembly. I believe the generated instruction encoding is right in the case shown below, but it might be a good idea to double-check. Cheers ---Dave binutils$ cat <<EOF >ldr-tst.s .syntax unified .globl d d: .quad 0 .type f, %function f: ldrd r0, r1, d nop ldrd r0, r1, d ldr r0, d nop ldr r0, d EOF binutils$ binutils/objdump -mthumb -o ldr-tst.o ldr-tst.s && arm-linux-gnueabi-objdump -dr ldr-tst.o [...] Disassembly of section .text: 00000000 <d>: ... 00000008 <f>: 8: e95f 0103 ldrd r0, r1, [pc, #-12] *** bug?: no label annotated c: 46c0 nop ; (mov r8, r8) e: e95f 0104 ldrd r0, r1, [pc, #-16] *** bug?: no label annotated 12: f85f 0014 ldr.w r0, [pc, #-20] ; 0 <d> 16: 46c0 nop ; (mov r8, r8) 18: f85f 001c ldr.w r0, [pc, #-28] ; 0 <d>
Hi Dave, I believe that this problem is fixed now. Please could you check locally and confirm ? Cheers Nick
(In reply to comment #1) > Hi Dave, > > I believe that this problem is fixed now. Please could you check locally and > confirm ? > > Cheers > Nick This doesn't seem to work for me. As before, the disassembly works as expected in ARM, but not in Thumb: binutils$ cat CVS/Root :pserver:anoncvs@sourceware.org/cvs/src binutils$ TZ= cvs -z6 update -D'2011-04-12 09:30' [...] binutils$ ./configure --build=x86_64-pc-linux-gnu --target=x86_64-pc-linux-gnu --target=arm-elf-eabi && make [...] binutils$ cat <<EOF >ldr-tst.s .syntax unified .globl d d: .quad 0 .type f, %function f: ldrd r0, r1, d nop ldrd r0, r1, d ldr r0, d nop ldr r0, d EOF binutils$ gas/as-new -mthumb -o ldr-tst.o ldr-tst.s ldr-tst.s: Assembler messages: ldr-tst.s:7: Error: cannot represent T32_OFFSET_IMM relocation in this object file format ldr-tst.s:9: Error: cannot represent T32_OFFSET_IMM relocation in this object file format ldr-tst.s:10: Error: cannot represent T32_OFFSET_IMM relocation in this object file format ldr-tst.s:12: Error: cannot represent T32_OFFSET_IMM relocation in this object file format binutils$ grep -v '\.globl' ldr-tst.s | gas/as-new -mthumb -o ldr-tst.o - binutils$ binutils/objdump -d ldr-tst.o ldr-tst.o: file format elf32-littlearm Disassembly of section .text: 00000000 <d>: ... 00000008 <f>: 8: e95f 0103 ldrd r0, r1, [pc, #-12] c: 46c0 nop ; (mov r8, r8) e: e95f 0104 ldrd r0, r1, [pc, #-16] 12: f85f 0014 ldr.w r0, [pc, #-20] ; 0 <d> 16: 46c0 nop ; (mov r8, r8) 18: f85f 001c ldr.w r0, [pc, #-28] ; 0 <d> binutils$ gas/as-new -mthumb -o ldr-tst.o ldr-tst.s ldr-tst.s: Assembler messages: ldr-tst.s:7: Error: cannot represent OFFSET_IMM8 relocation in this object file format ldr-tst.s:9: Error: cannot represent OFFSET_IMM8 relocation in this object file format binutils$ grep -v '\.globl' ldr-tst.s | gas/as-new -mthumb -o ldr-tst.o - binutils$ binutils/objdump -d ldr-tst.o ldr-tst.o: file format elf32-littlearm Disassembly of section .text: 00000000 <d>: ... 00000008 <f>: 8: e14f01d0 ldrd r0, [pc, #-16] ; 0 <d> c: e1a00000 nop ; (mov r0, r0) 10: e14f01d8 ldrd r0, [pc, #-24] ; 0 <d> 14: e51f001c ldr r0, [pc, #-28] ; 0 <d> 18: e1a00000 nop ; (mov r0, r0) 1c: e51f0024 ldr r0, [pc, #-36] ; 0 <d> binutils$ exit
Created attachment 5666 [details] Decode addresses used by LDRD and STRD insns.
Hi Dave, Please could you try out the uploaded patch and let me know if it works for you. Cheers Nick
(In reply to comment #4) > Hi Dave, > > Please could you try out the uploaded patch and let me know if it works for > you. > > Cheers > Nick Yes, that seems to work for me now. Cheers ---Dave Disassembly of section .text: 00000000 <d>: ... 00000008 <f>: 8: e95f 0103 ldrd r0, r1, [pc, #-12] ; 0 <d> c: 46c0 nop ; (mov r8, r8) e: e95f 0104 ldrd r0, r1, [pc, #-16] ; 0 <d> 12: f85f 0014 ldr.w r0, [pc, #-20] ; 0 <d> 16: 46c0 nop ; (mov r8, r8) 18: f85f 001c ldr.w r0, [pc, #-28] ; 0 <d>
CVSROOT: /cvs/src Module name: src Changes by: nickc@sourceware.org 2011-04-12 16:01:49 Modified files: opcodes : ChangeLog arm-dis.c gas/testsuite : ChangeLog gas/testsuite/gas/arm: thumb32.d thumb32.l thumb32.s Log message: PR binutils/12534 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn patterns. (print_insn_thumb32): Handle %L. * gas/arm/thumb32.s: Add PC relative LDRD and STRD insns. * gas/arm/thumb32.l: Update expected output. * gas/arm/thumb32.d: Update expected disassembly. Patches: http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1714&r2=1.1715 http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/arm-dis.c.diff?cvsroot=src&r1=1.140&r2=1.141 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1883&r2=1.1884 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb32.d.diff?cvsroot=src&r1=1.40&r2=1.41 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb32.l.diff?cvsroot=src&r1=1.3&r2=1.4 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/thumb32.s.diff?cvsroot=src&r1=1.19&r2=1.20
Patch (and testsuite update) checked in.