12296 2010-12-08 12:44:00 +0000 cortex-m3: SVC is not permitted on this architecture 2011-04-11 15:25:17 +0000 1 1 1 Unclassified binutils gas 2.21 All All RESOLVED FIXED P2 normal --- 1 enrico.scholz unassigned dan kseinitzer lancos mgretton nickc stano arm-linux-gnueabi 46350 enrico.scholz 2010-12-08 12:44:44 +0000 While building code like $ echo 'svc 0' > /tmp/x.s $ arm-linux-gnueabi-as -mcpu=cortex-m3 /tmp/x.s /tmp/x.s: Assembler messages: /tmp/x.s:1: Error: SVC is not permitted on this architecture 'svc' is a valid operation on Cortex-M3 cpus and code was accepted by previous binutils version. Report is against 63afe4ed46b5b8c21445192c9046d1c3de2859ec 46453 lancos 2010-12-17 22:42:05 +0000 I have the same issue while compiling freertos for cortex-m3 (that uses the 'svc 0' instruction) with binutils 2.21: "Error: SVC is not permitted on this architecture" building with binutils 2.20.1 works fine. 47665 5340 dan 2011-03-29 19:52:08 +0000 Created attachment 5340 update ARM_AEXT_V7_ARM macro to include ARM_OS_EXT flag This also affects target arm-none-eabi. Like Claudio, I am also trying to compile FreeRTOS. It looks like the v7 processor profile (which the Cortex-M3 is an example of) neglects to mark the "os" extension as being available. I attached a diff against CVS that fixes this issue for me. The patch updates the ARM_AEXT_V7_ARM macro to also include the ARM_OS_EXT flag. I believe that all v7 processors have the SVC instruction (based on the v7-M and v7-AR reference manuals). $ echo 'svc 0' > /tmp/x.s $ arm-none-eabi-as -mcpu=cortex-m3 /tmp/x.s -o /tmp/x.o $ arm-none-eabi-objdump -d /tmp/x.o /tmp/x.o: file format elf32-littlearm Disassembly of section .text: 00000000 <.text>: 0: df00 svc 0 47673 mgretton 2011-03-30 09:32:31 +0000 (In reply to comment #2) > It looks like the v7 processor profile (which the Cortex-M3 is an example of) > neglects to mark the "os" extension as being available. This is indeed the case. Mistake on my part when creating the initial patch. Please submit a patch - with testcase - to the binutils mailing list. 47703 5347 dan 2011-03-31 19:22:01 +0000 Created attachment 5347 Mark ARMv7 as having OS extension, add testcase, fix 1/5 regressions The previous patch introduced 5 test failure regressions. Failure #1: The patch somehow changed the armv7 attr table to include a new line, "Tag_CPU_arch_profile: Microcontroller". This new patch modifies the expect script to allow this change, but I don't know if this is correct behavior. Failures #2-5: Instructions of the form "msr APSR_<bits>,<imm|reg>" now generate syntax errors. Previously, using an immediate for the operand would generate a different error that was explicitly checked for, and registers as the second operand would assemble into valid instructions. I spent some time with it (I think the problem manifests in parse_operands(), but probably doesn't originate there) but this takes more effort that I can commit to figure out what is going wrong. This patch makes no attempt to fix these problems. Finally, this patch enhances a testcase to verify the svc instruction compiles correctly. 48198 cvs-commit 2011-04-11 15:23:12 +0000 CVSROOT: /cvs/src Module name: src Changes by: nickc@sourceware.org 2011-04-11 15:23:09 Modified files: gas/testsuite : ChangeLog gas/testsuite/gas/arm: arch7.d arch7.s attr-march-armv7.d include/opcode : ChangeLog arm.h Log message: PR gas/12296 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS. * gas/arm/arch7.s: Add SVC insn. * gas/arm/arch7.d: Add disassembly of SVC insn. * gas/arm/attr-march-armv7.d: Add arch profile tag. Patches: http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1879&r2=1.1880 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arch7.d.diff?cvsroot=src&r1=1.6&r2=1.7 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/arch7.s.diff?cvsroot=src&r1=1.2&r2=1.3 http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/arm/attr-march-armv7.d.diff?cvsroot=src&r1=1.3&r2=1.4 http://sourceware.org/cgi-bin/cvsweb.cgi/src/include/opcode/ChangeLog.diff?cvsroot=src&r1=1.435&r2=1.436 http://sourceware.org/cgi-bin/cvsweb.cgi/src/include/opcode/arm.h.diff?cvsroot=src&r1=1.24&r2=1.25 48199 Matthew.Gretton-Dann 2011-04-11 15:24:00 +0000 Hi, I am out of the office until Monday 18th April 2011, and will not be reading email. If you have an urgent issue please get in touch with Richard Earnshaw. Otherwise, I will get back to you as soon as possible after I am back in the office on Monday 18th April 2011. Thanks, Matt 48200 nickc 2011-04-11 15:24:41 +0000 Hi Dan, Thanks very much for revised patch. I have now checked it in along with these changelog entries. Cheers Nick include/opcode/ChangeLog 2011-04-11 Dan McDonald <dan@wellkeeper.com> PR gas/12296 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS. gas/testsuite/ChangeLog 2011-04-11 Dan McDonald <dan@wellkeeper.com> PR gas/12296 * gas/arm/arch7.s: Add SVC insn. * gas/arm/arch7.d: Add disassembly of SVC insn. * gas/arm/attr-march-armv7.d: Add arch profile tag. 48201 nickc 2011-04-11 15:25:17 +0000 patch applied 5340 2011-03-29 19:52:00 +0000 2011-03-31 19:22:01 +0000 update ARM_AEXT_V7_ARM macro to include ARM_OS_EXT flag armv7_has_os_ext.patch text/plain 834 dan PyBBUk12N19oYXNfb3NfZXh0LnBhdGNoCkluZGV4OiBpbmNsdWRlL29wY29kZS9hcm0uaAo9PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09ClJDUyBmaWxlOiAvY3ZzL3NyYy9zcmMvaW5jbHVkZS9vcGNvZGUvYXJtLmgsdgpyZXRy aWV2aW5nIHJldmlzaW9uIDEuMjQKZGlmZiAtdSAtcjEuMjQgYXJtLmgKLS0tIGluY2x1ZGUvb3Bj b2RlL2FybS5oCTE1IE5vdiAyMDEwIDEwOjAzOjA1IC0wMDAwCTEuMjQKKysrIGluY2x1ZGUvb3Bj b2RlL2FybS5oCTI5IE1hciAyMDExIDE5OjQ2OjA5IC0wMDAwCkBAIC0xMDksNyArMTA5LDggQEAK ICNkZWZpbmUgQVJNX0FFWFRfVjZLVDIgIChBUk1fQUVYVF9WNlQyIHwgQVJNX0VYVF9WNkspCiAj ZGVmaW5lIEFSTV9BRVhUX1Y2WlQyICAoQVJNX0FFWFRfVjZUMiB8IEFSTV9FWFRfU0VDKQogI2Rl ZmluZSBBUk1fQUVYVF9WNlpLVDIgKEFSTV9BRVhUX1Y2VDIgfCBBUk1fRVhUX1Y2SyB8IEFSTV9F WFRfU0VDKQotI2RlZmluZSBBUk1fQUVYVF9WN19BUk0JKEFSTV9BRVhUX1Y2S1QyIHwgQVJNX0VY VF9WNyB8IEFSTV9FWFRfQkFSUklFUikKKyNkZWZpbmUgQVJNX0FFWFRfVjdfQVJNCShBUk1fQUVY VF9WNktUMiB8IEFSTV9FWFRfVjcgfCBBUk1fRVhUX0JBUlJJRVIgXAorICAgIHwgQVJNX0VYVF9P UykKICNkZWZpbmUgQVJNX0FFWFRfVjdBCShBUk1fQUVYVF9WN19BUk0gfCBBUk1fRVhUX1Y3QSkK ICNkZWZpbmUgQVJNX0FFWFRfVjdSCShBUk1fQUVYVF9WN19BUk0gfCBBUk1fRVhUX1Y3UiB8IEFS TV9FWFRfRElWKQogI2RlZmluZSBBUk1fQUVYVF9OT1RNIFwK 5347 2011-03-31 19:22:00 +0000 2011-03-31 19:22:01 +0000 Mark ARMv7 as having OS extension, add testcase, fix 1/5 regressions patch-binutils-2.21-fix-12296.diff text/plain 2277 dan SW5kZXg6IGdhcy90ZXN0c3VpdGUvZ2FzL2FybS9hcmNoNy5kCj09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KUkNTIGZpbGU6 IC9jdnMvc3JjL3NyYy9nYXMvdGVzdHN1aXRlL2dhcy9hcm0vYXJjaDcuZCx2CnJldHJpZXZpbmcg cmV2aXNpb24gMS42CmRpZmYgLXUgLXIxLjYgYXJjaDcuZAotLS0gZ2FzL3Rlc3RzdWl0ZS9nYXMv YXJtL2FyY2g3LmQJMTcgU2VwIDIwMTAgMTA6NDI6MDQgLTAwMDAJMS42CisrKyBnYXMvdGVzdHN1 aXRlL2dhcy9hcm0vYXJjaDcuZAkzMCBNYXIgMjAxMSAyMjo0NDoxNyAtMDAwMApAQCAtNzYsMyAr NzYsNCBAQAogMCsxMGMgPFtePl0qPiBmMzgwIDg4MTQgCW1zcglDT05UUk9MLCByMAogMCsxMTAg PFtePl0qPiBmM2VmIDgwMDMgCW1ycwlyMCwgUFNSCiAwKzExNCA8W14+XSo+IGYzODAgODgwMyAJ bXNyCVBTUiwgcjAKKzArMTE4IDxbXj5dKj4gZGYwMCAgICAgIAlzdmMJMApJbmRleDogZ2FzL3Rl c3RzdWl0ZS9nYXMvYXJtL2FyY2g3LnMKPT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PQpSQ1MgZmlsZTogL2N2cy9zcmMvc3Jj L2dhcy90ZXN0c3VpdGUvZ2FzL2FybS9hcmNoNy5zLHYKcmV0cmlldmluZyByZXZpc2lvbiAxLjIK ZGlmZiAtdSAtcjEuMiBhcmNoNy5zCi0tLSBnYXMvdGVzdHN1aXRlL2dhcy9hcm0vYXJjaDcucwkx NyBTZXAgMjAxMCAxMDo0MjowNCAtMDAwMAkxLjIKKysrIGdhcy90ZXN0c3VpdGUvZ2FzL2FybS9h cmNoNy5zCTMwIE1hciAyMDExIDIyOjQ0OjE3IC0wMDAwCkBAIC03OSwzICs3OSw1IEBACiAJbXNy CWNvbnRyb2wsIHIwCiAJbXJzCXIwLCB4cHNyCiAJbXNyCXhwc3IsIHIwCisKKwlzdmMJMApJbmRl eDogZ2FzL3Rlc3RzdWl0ZS9nYXMvYXJtL2F0dHItbWFyY2gtYXJtdjcuZAo9PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09ClJD UyBmaWxlOiAvY3ZzL3NyYy9zcmMvZ2FzL3Rlc3RzdWl0ZS9nYXMvYXJtL2F0dHItbWFyY2gtYXJt djcuZCx2CnJldHJpZXZpbmcgcmV2aXNpb24gMS4zCmRpZmYgLXUgLXIxLjMgYXR0ci1tYXJjaC1h cm12Ny5kCi0tLSBnYXMvdGVzdHN1aXRlL2dhcy9hcm0vYXR0ci1tYXJjaC1hcm12Ny5kCTExIE1h eSAyMDEwIDE3OjM2OjMzIC0wMDAwCTEuMworKysgZ2FzL3Rlc3RzdWl0ZS9nYXMvYXJtL2F0dHIt bWFyY2gtYXJtdjcuZAkzMCBNYXIgMjAxMSAyMjo0NDoxNyAtMDAwMApAQCAtOSw1ICs5LDYgQEAK IEZpbGUgQXR0cmlidXRlcwogICBUYWdfQ1BVX25hbWU6ICI3IgogICBUYWdfQ1BVX2FyY2g6IHY3 CisgIFRhZ19DUFVfYXJjaF9wcm9maWxlOiBNaWNyb2NvbnRyb2xsZXIKICAgVGFnX1RIVU1CX0lT QV91c2U6IFRodW1iLTIKICAgVGFnX0RJVl91c2U6IE5vdCBhbGxvd2VkCkluZGV4OiBpbmNsdWRl L29wY29kZS9hcm0uaAo9PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09ClJDUyBmaWxlOiAvY3ZzL3NyYy9zcmMvaW5jbHVkZS9v cGNvZGUvYXJtLmgsdgpyZXRyaWV2aW5nIHJldmlzaW9uIDEuMjQKZGlmZiAtdSAtcjEuMjQgYXJt LmgKLS0tIGluY2x1ZGUvb3Bjb2RlL2FybS5oCTE1IE5vdiAyMDEwIDEwOjAzOjA1IC0wMDAwCTEu MjQKKysrIGluY2x1ZGUvb3Bjb2RlL2FybS5oCTMwIE1hciAyMDExIDIyOjQ0OjE4IC0wMDAwCkBA IC0xMDksNyArMTA5LDggQEAKICNkZWZpbmUgQVJNX0FFWFRfVjZLVDIgIChBUk1fQUVYVF9WNlQy IHwgQVJNX0VYVF9WNkspCiAjZGVmaW5lIEFSTV9BRVhUX1Y2WlQyICAoQVJNX0FFWFRfVjZUMiB8 IEFSTV9FWFRfU0VDKQogI2RlZmluZSBBUk1fQUVYVF9WNlpLVDIgKEFSTV9BRVhUX1Y2VDIgfCBB Uk1fRVhUX1Y2SyB8IEFSTV9FWFRfU0VDKQotI2RlZmluZSBBUk1fQUVYVF9WN19BUk0JKEFSTV9B RVhUX1Y2S1QyIHwgQVJNX0VYVF9WNyB8IEFSTV9FWFRfQkFSUklFUikKKyNkZWZpbmUgQVJNX0FF WFRfVjdfQVJNCShBUk1fQUVYVF9WNktUMiB8IEFSTV9FWFRfVjcgfCBBUk1fRVhUX0JBUlJJRVIg XAorICAgIHwgQVJNX0VYVF9PUykKICNkZWZpbmUgQVJNX0FFWFRfVjdBCShBUk1fQUVYVF9WN19B Uk0gfCBBUk1fRVhUX1Y3QSkKICNkZWZpbmUgQVJNX0FFWFRfVjdSCShBUk1fQUVYVF9WN19BUk0g fCBBUk1fRVhUX1Y3UiB8IEFSTV9FWFRfRElWKQogI2RlZmluZSBBUk1fQUVYVF9OT1RNIFwK