The i386 version of as has a few machine
dependent options:
--32 | --x32 | --64Select the word size, either 32 bits or 64 bits. ‘--32’ implies Intel i386 architecture, while ‘--x32’ and ‘--64’ imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.
These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add –enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).
-nBy default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment.
--divideOn SVR4-derived platforms, the character ‘/’ is treated as a comment character, which means that it cannot be used in expressions. The ‘--divide’ option turns ‘/’ into a normal character. This does not disable ‘/’ at the beginning of a line starting a comment, or affect using ‘#’ for starting a comment.
-march=CPU[+EXTENSION…]This option specifies the target processor. The assembler will
issue an error message if an attempt is made to assemble an instruction
which will not execute on the target processor. The following
processor names are recognized:
i8086,
i186,
i286,
i386,
i486,
i586,
i686,
pentium,
pentiumpro,
pentiumii,
pentiumiii,
pentium4,
prescott,
nocona,
core,
core2,
corei7,
iamcu,
k6,
k6_2,
athlon,
opteron,
k8,
amdfam10,
bdver1,
bdver2,
bdver3,
bdver4,
znver1,
znver2,
znver3,
znver4,
znver5,
btver1,
btver2,
generic32 and
generic64.
In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics. For example,
-march=i686+sse4+vmx extends i686 with sse4 and
vmx. The following extensions are currently supported:
8087,
287,
387,
687,
cmov,
fxsr,
mmx,
sse,
sse2,
sse3,
sse4a,
ssse3,
sse4.1,
sse4.2,
sse4,
avx,
avx2,
lahf_sahf,
monitor,
adx,
rdseed,
prfchw,
smap,
mpx,
sha,
rdpid,
ptwrite,
cet,
gfni,
vaes,
vpclmulqdq,
prefetchwt1,
clflushopt,
se1,
clwb,
movdiri,
movdir64b,
enqcmd,
serialize,
tsxldtrk,
kl,
widekl,
hreset,
avx512f,
avx512cd,
avx512er,
avx512pf,
avx512vl,
avx512bw,
avx512dq,
avx512ifma,
avx512vbmi,
avx512_4fmaps,
avx512_4vnniw,
avx512_vpopcntdq,
avx512_vbmi2,
avx512_vnni,
avx512_bitalg,
avx512_vp2intersect,
tdx,
avx512_bf16,
avx_vnni,
avx512_fp16,
prefetchi,
avx_ifma,
avx_vnni_int8,
cmpccxadd,
wrmsrns,
msrlist,
avx_ne_convert,
rao_int,
fred,
lkgs,
avx_vnni_int16,
sha512,
sm3,
sm4,
pbndkb,
avx10.1,
avx10.1/512,
avx10.1/256,
avx10.1/128,
user_msr,
apx_f,
amx_int8,
amx_bf16,
amx_fp16,
amx_complex,
amx_tile,
vmx,
vmfunc,
smx,
xsave,
xsaveopt,
xsavec,
xsaves,
aes,
pclmul,
fsgsbase,
rdrnd,
f16c,
bmi2,
fma,
movbe,
ept,
lzcnt,
popcnt,
hle,
rtm,
tsx,
invpcid,
clflush,
mwaitx,
clzero,
wbnoinvd,
pconfig,
waitpkg,
uintr,
cldemote,
rdpru,
mcommit,
sev_es,
lwp,
fma4,
xop,
cx16,
syscall,
rdtscp,
3dnow,
3dnowa,
sse4a,
sse5,
snp,
invlpgb,
tlbsync,
svme and
padlock.
Note that these extension mnemonics can be prefixed with no to revoke
the respective (and any dependent) functionality. Note further that the
suffixes permitted on -march=avx10.<N> enforce a vector length
restriction, i.e. despite these otherwise being "enabling" options, using
these suffixes will disable all insns with wider vector or mask register
operands.
When the .arch directive is used with -march, the
.arch directive will take precedent.
-mtune=CPUThis option specifies a processor to optimize for. When used in conjunction with the -march option, only instructions of the processor specified by the -march option will be generated.
Valid CPU values are identical to the processor list of -march=CPU.
-moperand-check=none-moperand-check=warning-moperand-check=errorThese options control if the assembler should check certain instruction operands or operand combinations. An example instructions where operand size cannot be inferred from its operands and also hasn’t been specified by way of an instruction suffix. -moperand-check=none will make the assembler not perform these checks. -moperand-check=warning will make the assembler issue a warning when respective checks fail, which is the default. -moperand-check=error will make the assembler issue an error when respective checks fail.
-msse2avxThis option specifies that the assembler should encode SSE instructions with VEX prefix, requiring AVX to be available. SSE instructions using extended GPRs will be encoded with EVEX prefix, requiring AVX512 or AVX10 to be available.
-muse-unaligned-vector-moveThis option specifies that the assembler should encode aligned vector move as unaligned vector move.
-msse-check=none-msse-check=warning-msse-check=errorThese options control if the assembler should check SSE instructions. -msse-check=none will make the assembler not to check SSE instructions, which is the default. -msse-check=warning will make the assembler issue a warning for any SSE instruction. -msse-check=error will make the assembler issue an error for any SSE instruction.
-mavxscalar=128-mavxscalar=256These options control how the assembler should encode scalar AVX instructions. -mavxscalar=128 will encode scalar AVX instructions with 128bit vector length, which is the default. -mavxscalar=256 will encode scalar AVX instructions with 256bit vector length.
WARNING: Don’t use this for production code - due to CPU errata the resulting code may not work on certain models.
-mvexwig=0-mvexwig=1These options control how the assembler should encode VEX.W-ignored (WIG) VEX instructions. -mvexwig=0 will encode WIG VEX instructions with vex.w = 0, which is the default. -mvexwig=1 will encode WIG EVEX instructions with vex.w = 1.
WARNING: Don’t use this for production code - due to CPU errata the resulting code may not work on certain models.
-mevexlig=128-mevexlig=256-mevexlig=512These options control how the assembler should encode length-ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG EVEX instructions with 128bit vector length, which is the default. -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions with 256bit and 512bit vector length, respectively.
-mevexwig=0-mevexwig=1These options control how the assembler should encode w-ignored (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEX instructions with evex.w = 0, which is the default. -mevexwig=1 will encode WIG EVEX instructions with evex.w = 1.
-mmnemonic=att-mmnemonic=intelThis option specifies instruction mnemonic for matching instructions.
The .att_mnemonic and .intel_mnemonic directives will
take precedent.
-msyntax=att-msyntax=intelThis option specifies instruction syntax when processing instructions.
The .att_syntax and .intel_syntax directives will
take precedent.
-mnaked-regThis option specifies that registers don’t require a ‘%’ prefix.
The .att_syntax and .intel_syntax directives will take precedent.
-madd-bnd-prefixThis option forces the assembler to add BND prefix to all branches, even if such prefix was not explicitly specified in the source code.
-mno-sharedOn ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The ‘-mshared’ option tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger. This option only affects the handling of branch instructions.
-mbig-objOn PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections.
-momit-lock-prefix=no-momit-lock-prefix=yesThese options control how the assembler should encode lock prefix. This option is intended as a workaround for processors, that fail on lock prefix. This option can only be safely used with single-core, single-thread computers -momit-lock-prefix=yes will omit all lock prefixes. -momit-lock-prefix=no will encode lock prefix as usual, which is the default.
-mfence-as-lock-add=no-mfence-as-lock-add=yesThese options control how the assembler should encode lfence, mfence and sfence. -mfence-as-lock-add=yes will encode lfence, mfence and sfence as ‘lock addl $0x0, (%rsp)’ in 64-bit mode and ‘lock addl $0x0, (%esp)’ in 32-bit mode. -mfence-as-lock-add=no will encode lfence, mfence and sfence as usual, which is the default.
-mrelax-relocations=no-mrelax-relocations=yesThese options control whether the assembler should generate relax relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX, in 64-bit mode. -mrelax-relocations=yes will generate relax relocations. -mrelax-relocations=no will not generate relax relocations. The default can be controlled by a configure option --enable-x86-relax-relocations.
-malign-branch-boundary=NUMThis option controls how the assembler should align branches with segment prefixes or NOP. NUM must be a power of 2. It should be 0 or no less than 16. Branches will be aligned within NUM byte boundary. -malign-branch-boundary=0, which is the default, doesn’t align branches.
-malign-branch=TYPE[+TYPE...]This option specifies types of branches to align. TYPE is combination of ‘jcc’, which aligns conditional jumps, ‘fused’, which aligns fused conditional jumps, ‘jmp’, which aligns unconditional jumps, ‘call’ which aligns calls, ‘ret’, which aligns rets, ‘indirect’, which aligns indirect jumps and calls. The default is -malign-branch=jcc+fused+jmp.
-malign-branch-prefix-size=NUMThis option specifies the maximum number of prefixes on an instruction to align branches. NUM should be between 0 and 5. The default NUM is 5.
-mbranches-within-32B-boundariesThis option aligns conditional jumps, fused conditional jumps and unconditional jumps within 32 byte boundary with up to 5 segment prefixes on an instruction. It is equivalent to -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5. The default doesn’t align branches.
-mlfence-after-load=no-mlfence-after-load=yesThese options control whether the assembler should generate lfence after load instructions. -mlfence-after-load=yes will generate lfence. -mlfence-after-load=no will not generate lfence, which is the default.
-mlfence-before-indirect-branch=none-mlfence-before-indirect-branch=all-mlfence-before-indirect-branch=register-mlfence-before-indirect-branch=memoryThese options control whether the assembler should generate lfence before indirect near branch instructions. -mlfence-before-indirect-branch=all will generate lfence before indirect near branch via register and issue a warning before indirect near branch via memory. It also implicitly sets -mlfence-before-ret=shl when there’s no explicit -mlfence-before-ret=. -mlfence-before-indirect-branch=register will generate lfence before indirect near branch via register. -mlfence-before-indirect-branch=memory will issue a warning before indirect near branch via memory. -mlfence-before-indirect-branch=none will not generate lfence nor issue warning, which is the default. Note that lfence won’t be generated before indirect near branch via register with -mlfence-after-load=yes since lfence will be generated after loading branch target register.
-mlfence-before-ret=none-mlfence-before-ret=shl-mlfence-before-ret=or-mlfence-before-ret=yes-mlfence-before-ret=notThese options control whether the assembler should generate lfence before ret. -mlfence-before-ret=or will generate generate or instruction with lfence. -mlfence-before-ret=shl/yes will generate shl instruction with lfence. -mlfence-before-ret=not will generate not instruction with lfence. -mlfence-before-ret=none will not generate lfence, which is the default.
-mx86-used-note=no-mx86-used-note=yesThese options control whether the assembler should generate GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes. The default can be controlled by the --enable-x86-used-note configure option.
-mevexrcig=rne-mevexrcig=rd-mevexrcig=ru-mevexrcig=rzThese options control how the assembler should encode SAE-only EVEX instructions. -mevexrcig=rne will encode RC bits of EVEX instruction with 00, which is the default. -mevexrcig=rd, -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX instructions with 01, 10 and 11 RC bits, respectively.
-mamd64-mintel64This option specifies that the assembler should accept only AMD64 or Intel64 ISA in 64-bit mode. The default is to accept common, Intel64 only and AMD64 ISAs.
-O0 | -O | -O1 | -O2 | -OsOptimize instruction encoding with smaller instruction size. ‘-O’ and ‘-O1’ encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates, encode 64-bit register clearing instructions with 32-bit register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions, encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions, and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical.
‘-O2’ includes ‘-O1’ optimization plus encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit EVEX vector register clearing instructions. In 64-bit mode VEX encoded instructions with commutative source operands will also have their source operands swapped if this allows using the 2-byte VEX prefix form instead of the 3-byte one. Certain forms of AND as well as OR with the same (register) operand specified twice will also be changed to TEST.
‘-Os’ includes ‘-O2’ optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. ‘-O0’ turns off this optimization.