The SPARC chip family includes several successive versions, using the same core instruction set, but including a few additional instructions at each version. There are exceptions to this however. For details on what instructions each variant supports, please see the chip’s architecture reference manual.
as assumes the core instruction set (SPARC
v6), but “bumps” the architecture level as needed: it switches to
successively higher architectures as it encounters instructions that
only exist in the higher levels.
If not configured for SPARC v9 (
sparc64-*-*) GAS will not bump
past sparclite by default, an option must be passed to enable the
GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested. SPARC v9 is always incompatible with sparclite.
-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |
-Av8plusv | -Av8plusm | -Av8plusm8
-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8
-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
-Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6
Use one of the ‘-A’ options to select one of the SPARC
architectures explicitly. If you select an architecture explicitly,
as reports a fatal error if it encounters an instruction
or feature requiring an incompatible or higher level.
‘-Av8plus’, ‘-Av8plusa’, ‘-Av8plusb’, ‘-Av8plusc’, ‘-Av8plusd’, and ‘-Av8plusv’ select a 32 bit environment.
‘-Av9’, ‘-Av9a’, ‘-Av9b’, ‘-Av9c’, ‘-Av9d’, ‘-Av9e’, ‘-Av9v’ and ‘-Av9m’ select a 64 bit environment and are not available unless GAS is explicitly configured with 64 bit environment support.
‘-Av8plusa’ and ‘-Av9a’ enable the SPARC V9 instruction set with UltraSPARC VIS 1.0 extensions.
‘-Av8plusb’ and ‘-Av9b’ enable the UltraSPARC VIS 2.0 instructions, as well as the instructions enabled by ‘-Av8plusa’ and ‘-Av9a’.
‘-Av8plusc’ and ‘-Av9c’ enable the UltraSPARC Niagara instructions, as well as the instructions enabled by ‘-Av8plusb’ and ‘-Av9b’.
‘-Av8plusd’ and ‘-Av9d’ enable the floating point fused multiply-add, VIS 3.0, and HPC extension instructions, as well as the instructions enabled by ‘-Av8plusc’ and ‘-Av9c’.
‘-Av8pluse’ and ‘-Av9e’ enable the cryptographic instructions, as well as the instructions enabled by ‘-Av8plusd’ and ‘-Av9d’.
‘-Av8plusv’ and ‘-Av9v’ enable floating point unfused multiply-add, and integer multiply-add, as well as the instructions enabled by ‘-Av8pluse’ and ‘-Av9e’.
‘-Av8plusm’ and ‘-Av9m’ enable the VIS 4.0, subtract extended, xmpmul, xmontmul and xmontsqr instructions, as well as the instructions enabled by ‘-Av8plusv’ and ‘-Av9v’.
‘-Av8plusm8’ and ‘-Av9m8’ enable the instructions introduced in the Oracle SPARC Architecture 2017 and the M8 processor, as well as the instructions enabled by ‘-Av8plusm’ and ‘-Av9m’.
‘-Asparc’ specifies a v9 environment. It is equivalent to ‘-Av9’ if the word size is 64-bit, and ‘-Av8plus’ otherwise.
‘-Asparcvis’ specifies a v9a environment. It is equivalent to ‘-Av9a’ if the word size is 64-bit, and ‘-Av8plusa’ otherwise.
‘-Asparcvis2’ specifies a v9b environment. It is equivalent to ‘-Av9b’ if the word size is 64-bit, and ‘-Av8plusb’ otherwise.
‘-Asparcfmaf’ specifies a v9b environment with the floating point fused multiply-add instructions enabled.
‘-Asparcima’ specifies a v9b environment with the integer multiply-add instructions enabled.
‘-Asparcvis3’ specifies a v9b environment with the VIS 3.0, HPC , and floating point fused multiply-add instructions enabled.
‘-Asparcvis3r’ specifies a v9b environment with the VIS 3.0, HPC, and floating point unfused multiply-add instructions enabled.
‘-Asparc5’ is equivalent to ‘-Av9m’.
‘-Asparc6’ is equivalent to ‘-Av9m8’.
-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |
-xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b
-xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v
-xarch=v9m | -xarch=v9m8
-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
-xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6
For compatibility with the SunOS v9 assembler. These options are equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, -Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and -Asparc6 respectively.
Warn whenever it is necessary to switch to another level. If an architecture level is explicitly requested, GAS will not issue warnings until that level is reached, and will then bump the level as required (except between incompatible levels).
-32 | -64
Select the word size, either 32 bits or 64 bits. These options are only available with the ELF object file format, and require that the necessary BFD support has been included.
Warn if a DCTI (delayed control transfer instruction) couple is found when generating code for a variant of the SPARC architecture in which the execution of the couple is unpredictable, or very slow. This is disabled by default.