as for MIPS architectures supports several
different MIPS processors, and MIPS ISA levels I through V, MIPS32,
and MIPS64. For information about the MIPS instruction set, see
MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall).
For an overview of MIPS assembly conventions, see “Appendix D:
Assembly Language Programming” in the same work.