The ARC version of
as supports the following additional
ld. The optional third parameter, alignment, specifies the desired alignment of the symbol in the bss section, specified as a byte boundary (for example, an alignment of 16 means that the least significant 4 bits of the address should be zero). The alignment must be an absolute expression, and it must be a power of two. If no alignment is specified, as will set the alignment to the largest power of two less than or equal to the size of the symbol, up to a maximum of 16.
.cpudirective must be followed by the desired core version. Permitted values for CPU are:
.cpu directive overrides the command line option
-mcpu=cpu; a warning is emitted when the version is not
consistent between the two.
.extAuxRegister mulhi, 0x12, w
specifies a write only extension auxiliary register, mulhi at
.extCondCode is_busy,0x14 add.is_busy r1,r2,r3
will only execute the
add instruction if the condition code
value is 0x14.
The final parameter, shortcut indicates whether the register has a short cut in the pipeline. The valid values are:
.extCoreRegister mlo, 57, r , can_shortcut
defines a read only extension core register,
mlo, which is
register 57, and can short cut the pipeline.
The first argument, name, gives the name of the instruction.
The second argument, opcode, is the opcode to be used (bits 31:27 in the encoding).
The third argument, subopcode, is the sub-opcode to be used, but the correct value also depends on the fifth argument, syntaxclass
The fourth argument, suffixclass, determines the kinds of suffixes to be allowed. Valid values are:
The fifth and final argument, syntaxclass, determines the syntax class for the instruction. It can have the following values:
The syntax class may be followed by `|' and one of the following modifiers.
SYNTAX_3OP, specifying that the first operand of a three-operand instruction must be an immediate (i.e., the result is discarded). This is usually used to set the flags using specific instructions and not retain results.
SYNTAX_20P, specifying that there is an implied immediate destination operand which does not appear in the syntax.
For example, if the source code contains an instruction like:
the first argument is an implied immediate (that is, the result is discarded). This is the same as though the source code were: inst 0,r1,r2.
For example, defining a 64-bit multiplier with immediate operands:
.extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, SYNTAX_3OP|OP1_MUST_BE_IMM
which specifies an extension instruction named
mp64 with 3
operands. It sets the flags and can be used with a condition code,
for which the first operand is an immediate, i.e. equivalent to
discarding the result of the operation.
A two operands instruction variant would be:
.extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
which describes a two operand instruction with an implicit first immediate operand. The result of this operation would be discarded.