as implements all the standard AArch64 opcodes. It also
implements several pseudo opcodes, including several synthetic load
ldr <register> , =<expression>
The constant expression will be placed into the nearest literal pool (if it not already there) and a PC-relative LDR instruction will be generated.
For more information on the AArch64 instruction set and assembly language notation, see `ARMv8 Instruction Set Overview' available at http://infocenter.arm.com.