The SPARC chip family includes several successive versions, using the same core instruction set, but including a few additional instructions at each version. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.
as assumes the core instruction set (SPARC
v6), but “bumps” the architecture level as needed: it switches to
successively higher architectures as it encounters instructions that
only exist in the higher levels.
If not configured for SPARC v9 (
sparc64-*-*) GAS will not bump
past sparclite by default, an option must be passed to enable the
GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested. SPARC v9 is always incompatible with sparclite.
-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v
-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
-Asparcvis3 | -Asparcvis3r
asreports a fatal error if it encounters an instruction or feature requiring an incompatible or higher level.
`-Av8plus', `-Av8plusa', `-Av8plusb', `-Av8plusc', `-Av8plusd', and `-Av8plusv' select a 32 bit environment.
`-Av9', `-Av9a', `-Av9b', `-Av9c', `-Av9d', and `-Av9v' select a 64 bit environment and are not available unless GAS is explicitly configured with 64 bit environment support.
`-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with UltraSPARC VIS 1.0 extensions.
`-Av8plusb' and `-Av9b' enable the UltraSPARC VIS 2.0 instructions, as well as the instructions enabled by `-Av8plusa' and `-Av9a'.
`-Av8plusc' and `-Av9c' enable the UltraSPARC Niagara instructions, as well as the instructions enabled by `-Av8plusb' and `-Av9b'.
`-Av8plusd' and `-Av9d' enable the floating point fused multiply-add, VIS 3.0, and HPC extension instructions, as well as the instructions enabled by `-Av8plusc' and `-Av9c'.
`-Av8plusv' and `-Av9v' enable the 'random', transactional memory, floating point unfused multiply-add, integer multiply-add, and cache sparing store instructions, as well as the instructions enabled by `-Av8plusd' and `-Av9d'.
`-Asparc' specifies a v9 environment. It is equivalent to `-Av9' if the word size is 64-bit, and `-Av8plus' otherwise.
`-Asparcvis' specifies a v9a environment. It is equivalent to `-Av9a' if the word size is 64-bit, and `-Av8plusa' otherwise.
`-Asparcvis2' specifies a v9b environment. It is equivalent to `-Av9b' if the word size is 64-bit, and `-Av8plusb' otherwise.
`-Asparcfmaf' specifies a v9b environment with the floating point fused multiply-add instructions enabled.
`-Asparcima' specifies a v9b environment with the integer multiply-add instructions enabled.
`-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC , and floating point fused multiply-add instructions enabled.
`-Asparcvis3r' specifies a v9b environment with the VIS 3.0,
HPC, transactional memory, random, and floating point unfused multiply-add
-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
-xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
-xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v
-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
-32 | -64