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9.13.1 Options

The i386 version of as has a few machine dependent options:

--32 | --64
Select the word size, either 32 bits or 64 bits. Selecting 32-bit implies Intel i386 architecture, while 64-bit implies AMD x86-64 architecture.

These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add –enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).

By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization.

On SVR4-derived platforms, the character `/' is treated as a comment character, which means that it cannot be used in expressions. The `--divide' option turns `/' into a normal character. This does not disable `/' at the beginning of a line starting a comment, or affect using `#' for starting a comment.

This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7, l1om, k6, k6_2, athlon, opteron, k8, amdfam10, bdver1, generic32 and generic64.

In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics. For example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. The following extensions are currently supported: 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx, vmx, smx, xsave, xsaveopt, aes, pclmul, fsgsbase, rdrnd, f16c, fma, movbe, ept, clflush, lwp, fma4, xop, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, svme, abm and padlock. Note that rather than extending a basic instruction set, the extension mnemonics starting with no revoke the respective functionality.

When the .arch directive is used with -march, the .arch directive will take precedent.

This option specifies a processor to optimize for. When used in conjunction with the -march option, only instructions of the processor specified by the -march option will be generated.

Valid CPU values are identical to the processor list of -march=CPU.

This option specifies that the assembler should encode SSE instructions with VEX prefix.

These options control if the assembler should check SSE intructions. -msse-check=none will make the assembler not to check SSE instructions, which is the default. -msse-check=warning will make the assembler issue a warning for any SSE intruction. -msse-check=error will make the assembler issue an error for any SSE intruction.

This options control how the assembler should encode scalar AVX instructions. -mavxscalar=128 will encode scalar AVX instructions with 128bit vector length, which is the default. -mavxscalar=256 will encode scalar AVX instructions with 256bit vector length.

This option specifies instruction mnemonic for matching instructions. The .att_mnemonic and .intel_mnemonic directives will take precedent.

This option specifies instruction syntax when processing instructions. The .att_syntax and .intel_syntax directives will take precedent.

This opetion specifies that registers don't require a `%' prefix. The .att_syntax and .intel_syntax directives will take precedent.