8. Machine Dependent Features

The machine instruction sets are (almost by definition) different on each machine where as runs. Floating point representations vary as well, and as often supports a few additional directives or command-line options for compatibility with other assemblers on a particular platform. Finally, some versions of as support special pseudo-instructions for branch optimization.

This chapter discusses most of these differences, though it does not include details on any machine's instruction set. For details on that subject, see the hardware manufacturer's manual.

8.2 AMD 29K Dependent Features
8.1 ARC Dependent Features
8.3 ARM Dependent Features
8.4 D10V Dependent Features
8.5 D30V Dependent Features
8.6 H8/300 Dependent Features		Hitachi H8/300 Dependent Features
8.7 H8/500 Dependent Features		Hitachi H8/500 Dependent Features
8.8 HPPA Dependent Features
8.9 ESA/390 Dependent Features		IBM ESA/390 Dependent Features
8.10 80386 Dependent Features		Intel 80386 Dependent Features
8.11 Intel 80960 Dependent Features
8.12 M680x0 Dependent Features
8.13 MIPS Dependent Features
8.15 Hitachi SH Dependent Features
8.14 picoJava Dependent Features
8.16 SPARC Dependent Features
8.19 v850 Dependent Features		V850 Dependent Features
8.17 Z8000 Dependent Features
8.18 VAX Dependent Features

8.1 ARC Dependent Features

8.1.1 Options
8.1.2 Floating Point
8.1.3 ARC Machine Directives		Sparc Machine Directives

8.1.1 Options

The ARC chip family includes several successive levels (or other variants) of chip, using the same core instruction set, but including a few additional instructions at each level.

By default, as assumes the core instruction set (ARC base). The .cpu pseudo-op is intended to be used to select the variant.

-mbig-endian

-mlittle-endian

Any ARC configuration of as can select big-endian or little-endian output at run time (unlike most other GNU development tools, which must be configured for one or the other). Use `-mbig-endian' to select big-endian output, and `-mlittle-endian' for little-endian.

8.1.2 Floating Point

The ARC cpu family currently does not have hardware floating point support. Software floating point support is provided by GCC and uses IEEE floating-point numbers.

8.1.3 ARC Machine Directives

The ARC version of as supports the following additional machine directives:

.cpu

This must be followed by the desired cpu. The ARC is intended to be customizable, .cpu is used to select the desired variant [though currently there are none].

8.2 AMD 29K Dependent Features

8.2.1 Options
8.2.2 Syntax
8.2.3 Floating Point
8.2.4 AMD 29K Machine Directives
8.2.5 Opcodes

8.2.1 Options

8.2.2 Syntax

8.2.2.1 Macros
8.2.2.2 Special Characters
8.2.2.3 Register Names

8.2.2.1 Macros

The macro syntax used on the AMD 29K is like that described in the AMD 29K Family Macro Assembler Specification. Normal as macros should still work.

8.2.2.2 Special Characters

`;' is the line comment character.

The character `?' is permitted in identifiers (but may not begin an identifier).

8.2.2.3 Register Names

General-purpose registers are represented by predefined symbols of the form `GRnnn' (for global registers) or `LRnnn' (for local registers), where nnn represents a number between 0 and 127, written with no leading zeros. The leading letters may be in either upper or lower case; for example, `gr13' and `LR7' are both valid register names.

You may also refer to general-purpose registers by specifying the register number as the result of an expression (prefixed with `%%' to flag the expression as a register number):

%%expression

---where expression must be an absolute expression evaluating to a number between 0 and 255. The range [0, 127] refers to global registers, and the range [128, 255] to local registers.

In addition, as understands the following protected special-purpose register names for the AMD 29K family:

vab chd pc0 ops chc pc1 cps rbp pc2 cfg tmc mmu cha tmr lru

These unprotected special-purpose register names are also recognized:

ipc alu fpe ipa bp inte ipb fc fps q cr exop

8.2.3 Floating Point

The AMD 29K family uses IEEE floating-point numbers.

8.2.4 AMD 29K Machine Directives

.block size , fill

This directive emits size bytes, each of value fill. Both size and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero.

In other versions of the GNU assembler, this directive is called `.space'.

.cputype

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.file

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

Warning: in other versions of the GNU assembler, .file is used for the directive called .app-file in the AMD 29K support.

.line

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.sect

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.use section name

Establishes the section and subsection for the following code; section name may be one of .text, .data, .data1, or .lit. With one of the first three section name options, `.use' is equivalent to the machine directive section name; the remaining case, `.use .lit', is the same as `.data 200'.

8.2.5 Opcodes

as implements all the standard AMD 29K opcodes. No additional pseudo-instructions are needed on this family.

For information on the 29K machine instruction set, see Am29000 User's Manual, Advanced Micro Devices, Inc.

8.3 ARM Dependent Features

8.3.1 Options
8.3.2 Syntax
8.3.3 Floating Point
8.3.4 ARM Machine Directives
8.3.5 Opcodes

8.3.1 Options

-marm[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]

This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor.

-marmv[2|2a|3|3m|4|4t|5|5t]

This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture.

-mthumb

This option specifies that only Thumb instructions should be assembled.

-mall

This option specifies that any Arm or Thumb instruction should be assembled.

-mfpa [10|11]

This option specifies the floating point architecture in use on the target processor.

-mfpe-old

Do not allow the assemble of floating point multiple instructions.

-mno-fpu

Do not allow the assembly of any floating point instructions.

-mthumb-interwork

This option specifies that the output generated by the assembler should be marked as supporting interworking.

-mapcs [26|32]

This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard.

-mapcs-float

This indicates the the floating point variant of the APCS should be used. In this variant floating point arguments are passed in FP registers rather than integer registers.

-mapcs-reentrant

This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code.

-EB

This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

-EL

This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.

-k

This option enables the generation of PIC (position independent code).

-moabi

This indicates that the code should be assembled using the old ARM ELF conventions, based on a beta release release of the ARM-ELF specifications, rather than the default conventions which are based on the final release of the ARM-ELF specifications.

8.3.2 Syntax

8.3.2.1 Special Characters
8.3.2.2 Register Names

8.3.2.1 Special Characters

The presence of a `@' on a line indicates the start of a comment that extends to the end of the current line. If a `#' appears as the first character of a line, the whole line is treated as a comment.

On ARM systems running the GNU/Linux operating system, `;' can be used instead of a newline to separate statements.

Either `#' or `$' can be used to indicate immediate operands.

*TODO* Explain about /data modifier on symbols.

8.3.2.2 Register Names

*TODO* Explain about ARM register naming, and the predefined names.

8.3.3 Floating Point

The ARM family uses IEEE floating-point numbers.

8.3.4 ARM Machine Directives

.align expression [, expression]

This is the generic .align directive. For the ARM however if the first argument is zero (ie no alignment is needed) the assembler will behave as if the argument had been 2 (ie pad to the next four byte boundary). This is for compatability with ARM's own assembler.

name .req register name

This creates an alias for register name called name. For example:

foo .req r0

.code [16|32]

This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.

.thumb

This performs the same action as .code 16.

.arm

This performs the same action as .code 32.

.force_thumb

This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions

.thumb_func

This directive specifies that the following symbol is the name of a Thumb encoded function. This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed.

.thumb_set

This performs the equivalent of a .set directive in that it creates a symbol which is an alias for another symbol (possibly not yet defined). This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point, in the same way that the .thumb_func directive does.

.ltorg

This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary).

.pool

This is a synonym for .ltorg.

8.3.5 Opcodes

as implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load instructions.

NOP

nop

This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0.

LDR

ldr <register> , = <expression>

If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions. Otherwise the constant will be placed into the nearest literal pool (if it not already there) and a PC relative LDR instruction will be generated.

ADR

adr <register> <label>

This instruction will load the address of label into the indicated register. The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located. If the label is out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool.

ADRL

adrl <register> <label>

This instruction will load the address of label into the indicated register. The instruction will evaluate to one or two a PC relative ADD or SUB instructions depending upon where the label is located. If a second instruction is not needed a NOP instruction will be generated in its place, so that this instruction is always 8 bytes long.

If the label is out of range, or if it is not defined in the same file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool.

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.

8.4 D10V Dependent Features

8.4.1 D10V Options
8.4.2 Syntax
8.4.3 Floating Point
8.4.4 Opcodes

8.4.1 D10V Options

`-O'

The D10V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.

`--nowarnswap'

To optimize execution performance, as will sometimes swap the order of instructions. Normally this generates a warning. When this option is used, no warning will be generated when instructions are swapped.

8.4.2 Syntax

The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. The differences are detailed below.

8.4.2.1 Size Modifiers
8.4.2.2 Sub-Instructions
8.4.2.3 Special Characters
8.4.2.4 Register Names
8.4.2.5 Addressing Modes
8.4.2.6 @WORD Modifier

8.4.2.1 Size Modifiers

8.4.2.2 Sub-Instructions

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

8.4.2.3 Special Characters

`->'

Sequential with instruction on the left first.

`<-'

Sequential with instruction on the right first.

`||'

Parallel

abs a1 -> abs r0

Execute these sequentially. The instruction on the right is in the right container and is executed second.

abs r0 <- abs a1

Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.

ld2w r2,@r8+ || mac a0,r0,r7

Execute these in parallel.

ld2w r2,@r8+ ||

mac a0,r0,r7

Two-line format. Execute these in parallel.

ld2w r2,@r8+

mac a0,r0,r7

Two-line format. Execute these sequentially. Assembler will put them in the proper containers.

ld2w r2,@r8+ ->

mac a0,r0,r7

Two-line format. Execute these sequentially. Same as above but second instruction will always go into right container.

8.4.2.4 Register Names

Register Pairs

r0-r1

r2-r3

r4-r5

r6-r7

r8-r9

r10-r11

r12-r13

r14-r15

The D10V also has predefined symbols for these control registers and status bits:

psw

Processor Status Word

bpsw

Backup Processor Status Word

pc

Program Counter

bpc

Backup Program Counter

rpt_c

Repeat Count

rpt_s

Repeat Start address

rpt_e

Repeat End address

mod_s

Modulo Start address

mod_e

Modulo End address

iba

Instruction Break Address

f0

Flag 0

f1

Flag 1

c

Carry flag

8.4.2.5 Addressing Modes

Rn

Register direct

@Rn

Register indirect

@Rn+

Register indirect with post-increment

@Rn-

Register indirect with post-decrement

@-SP

Register indirect with pre-decrement

@(disp, Rn)

Register indirect with displacement

addr

PC relative address (for branch or rep).

#imm

Immediate data (the `#' is optional and ignored)

8.4.2.6 @WORD Modifier

ldi     r2, main@word
jmp     r2

8.4.3 Floating Point

8.4.4 Opcodes

8.5 D30V Dependent Features

8.5.1 D30V Options
8.5.2 Syntax
8.5.3 Floating Point
8.5.4 Opcodes

8.5.1 D30V Options

`-O'

The D30V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.

`-n'

When this option is used, as will issue a warning every time it adds a nop instruction.

`-N'

When this option is used, as will issue a warning if it needs to insert a nop after a 32-bit multiply before a load or 16-bit multiply instruction.

8.5.2 Syntax

The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. The differences are detailed below.

8.5.2.1 Size Modifiers
8.5.2.2 Sub-Instructions
8.5.2.3 Special Characters
8.5.2.4 Guarded Execution
8.5.2.5 Register Names
8.5.2.6 Addressing Modes

8.5.2.1 Size Modifiers

8.5.2.2 Sub-Instructions

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

8.5.2.3 Special Characters

To specify the executing order, use the following symbols:

`->'

Sequential with instruction on the left first.

`<-'

Sequential with instruction on the right first.

`||'

Parallel

The D30V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example

abs r2,r3 -> abs r4,r5

Execute these sequentially. The instruction on the right is in the right container and is executed second.

abs r2,r3 <- abs r4,r5

Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.

abs r2,r3 || abs r4,r5

Execute these in parallel.

ldw r2,@(r3,r4) ||

mulx r6,r8,r9

Two-line format. Execute these in parallel.

mulx a0,r8,r9

stw r2,@(r3,r4)

Two-line format. Execute these sequentially unless `-O' option is used. If the `-O' option is used, the assembler will determine if the instructions could be done in parallel (the above two instructions can be done in parallel), and if so, emit them as parallel instructions. The assembler will put them in the proper containers. In the above example, the assembler will put the `stw' instruction in left container and the `mulx' instruction in the right container.

stw r2,@(r3,r4) ->

mulx a0,r8,r9

Two-line format. Execute the `stw' instruction followed by the `mulx' instruction sequentially. The first instruction goes in the left container and the second instruction goes into right container. The assembler will give an error if the machine ordering constraints are violated.

stw r2,@(r3,r4) <-

mulx a0,r8,r9

Same as previous example, except that the `mulx' instruction is executed before the `stw' instruction.

Since `$' has no special meaning, you may use it in symbol names.

8.5.2.4 Guarded Execution

`/tx'

Execute the instruction if flag f0 is true.

`/fx'

Execute the instruction if flag f0 is false.

`/xt'

Execute the instruction if flag f1 is true.

`/xf'

Execute the instruction if flag f1 is false.

`/tt'

Execute the instruction if both flags f0 and f1 are true.

`/tf'

Execute the instruction if flag f0 is true and flag f1 is false.

8.5.2.5 Register Names

The D30V also has predefined symbols for these control registers and status bits:

psw

Processor Status Word

bpsw

Backup Processor Status Word

pc

Program Counter

bpc

Backup Program Counter

rpt_c

Repeat Count

rpt_s

Repeat Start address

rpt_e

Repeat End address

mod_s

Modulo Start address

mod_e

Modulo End address

iba

Instruction Break Address

f0

Flag 0

f1

Flag 1

f2

Flag 2

f3

Flag 3

f4

Flag 4

f5

Flag 5

f6

Flag 6

f7

Flag 7

s

Same as flag 4 (saturation flag)

v

Same as flag 5 (overflow flag)

va

Same as flag 6 (sticky overflow flag)

c

Same as flag 7 (carry/borrow flag)

b

Same as flag 7 (carry/borrow flag)

8.5.2.6 Addressing Modes

Rn

Register direct

@Rn

Register indirect

@Rn+

Register indirect with post-increment

@Rn-

Register indirect with post-decrement

@-SP

Register indirect with pre-decrement

@(disp, Rn)

Register indirect with displacement

addr

PC relative address (for branch or rep).

#imm

Immediate data (the `#' is optional and ignored)

8.5.3 Floating Point

8.5.4 Opcodes

8.6 H8/300 Dependent Features

8.6.1 Options
8.6.2 Syntax
8.6.3 Floating Point
8.6.4 H8/300 Machine Directives
8.6.5 Opcodes

8.6.1 Options

as has no additional command-line options for the Hitachi H8/300 family.

8.6.2 Syntax

8.6.2.1 Special Characters
8.6.2.2 Register Names
8.6.2.3 Addressing Modes

8.6.2.1 Special Characters

`;' is the line comment character.

`$' can be used instead of a newline to separate statements. Therefore you may not use `$' in symbol names on the H8/300.

8.6.2.2 Register Names

You can use predefined symbols of the form `rnh' and `rnl' to refer to the H8/300 registers as sixteen 8-bit general-purpose registers. n is a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid register names.

You can also use the eight predefined symbols `rn' to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing).

On the H8/300H, you can also use the eight predefined symbols `ern' (`er0' ... `er7') to refer to the 32-bit general purpose registers.

The two control registers are called pc (program counter; a 16-bit register, except on the H8/300H where it is 24 bits) and ccr (condition code register; an 8-bit register). r7 is used as the stack pointer, and can also be called sp.

8.6.2.3 Addressing Modes

as understands the following addressing modes for the H8/300:

rn

Register direct

@rn

Register indirect

@(d, rn)

@(d:16, rn)

@(d:24, rn)

Register indirect: 16-bit or 24-bit displacement d from register n. (24-bit displacements are only meaningful on the H8/300H.)

@rn+

Register indirect with post-increment

@-rn

Register indirect with pre-decrement

@aa

@aa:8

@aa:16

@aa:24

Absolute address aa. (The address size `:24' only makes sense on the H8/300H.)

#xx

#xx:8

#xx:16

#xx:32

Immediate data xx. You may specify the `:8', `:16', or `:32' for clarity, if you wish; but as neither requires this nor uses it--the data size required is taken from context.

@@aa

@@aa:8

Memory indirect. You may specify the `:8' for clarity, if you wish; but as neither requires this nor uses it.

8.6.3 Floating Point

The H8/300 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

8.6.4 H8/300 Machine Directives

as has only one machine-dependent directive for the H8/300:

.h8300h

Recognize and emit additional instructions for the H8/300H variant, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

On the H8/300 family (including the H8/300H) `.word' directives generate 16-bit numbers.

8.6.5 Opcodes

For detailed information on the H8/300 machine instruction set, see H8/300 Series Programming Manual (Hitachi ADE--602--025). For information specific to the H8/300H, see H8/300H Series Programming Manual (Hitachi).

as implements all the standard H8/300 opcodes. No additional pseudo-instructions are needed on this family.

The following table summarizes the H8/300 opcodes, and their arguments. Entries marked `*' are opcodes used only on the H8/300H.

Legend: Rs source register Rd destination register abs absolute address imm immediate data disp:N N-bit displacement from a register pcrel:N N-bit displacement relative to program counter add.b #imm,rd * andc #imm,ccr add.b rs,rd band #imm,rd add.w rs,rd band #imm,@rd * add.w #imm,rd band #imm,@abs:8 * add.l rs,rd bra pcrel:8 * add.l #imm,rd * bra pcrel:16 adds #imm,rd bt pcrel:8 addx #imm,rd * bt pcrel:16 addx rs,rd brn pcrel:8 and.b #imm,rd * brn pcrel:16 and.b rs,rd bf pcrel:8 * and.w rs,rd * bf pcrel:16 * and.w #imm,rd bhi pcrel:8 * and.l #imm,rd * bhi pcrel:16 * and.l rs,rd bls pcrel:8 * bls pcrel:16 bld #imm,rd bcc pcrel:8 bld #imm,@rd * bcc pcrel:16 bld #imm,@abs:8 bhs pcrel:8 bnot #imm,rd * bhs pcrel:16 bnot #imm,@rd bcs pcrel:8 bnot #imm,@abs:8 * bcs pcrel:16 bnot rs,rd blo pcrel:8 bnot rs,@rd * blo pcrel:16 bnot rs,@abs:8 bne pcrel:8 bor #imm,rd * bne pcrel:16 bor #imm,@rd beq pcrel:8 bor #imm,@abs:8 * beq pcrel:16 bset #imm,rd bvc pcrel:8 bset #imm,@rd * bvc pcrel:16 bset #imm,@abs:8 bvs pcrel:8 bset rs,rd * bvs pcrel:16 bset rs,@rd bpl pcrel:8 bset rs,@abs:8 * bpl pcrel:16 bsr pcrel:8 bmi pcrel:8 bsr pcrel:16 * bmi pcrel:16 bst #imm,rd bge pcrel:8 bst #imm,@rd * bge pcrel:16 bst #imm,@abs:8 blt pcrel:8 btst #imm,rd * blt pcrel:16 btst #imm,@rd bgt pcrel:8 btst #imm,@abs:8 * bgt pcrel:16 btst rs,rd ble pcrel:8 btst rs,@rd * ble pcrel:16 btst rs,@abs:8 bclr #imm,rd bxor #imm,rd bclr #imm,@rd bxor #imm,@rd bclr #imm,@abs:8 bxor #imm,@abs:8 bclr rs,rd cmp.b #imm,rd bclr rs,@rd cmp.b rs,rd bclr rs,@abs:8 cmp.w rs,rd biand #imm,rd cmp.w rs,rd biand #imm,@rd * cmp.w #imm,rd biand #imm,@abs:8 * cmp.l #imm,rd bild #imm,rd * cmp.l rs,rd bild #imm,@rd daa rs bild #imm,@abs:8 das rs bior #imm,rd dec.b rs bior #imm,@rd * dec.w #imm,rd bior #imm,@abs:8 * dec.l #imm,rd bist #imm,rd divxu.b rs,rd bist #imm,@rd * divxu.w rs,rd bist #imm,@abs:8 * divxs.b rs,rd bixor #imm,rd * divxs.w rs,rd bixor #imm,@rd eepmov bixor #imm,@abs:8 * eepmovw * exts.w rd mov.w rs,@abs:16 * exts.l rd * mov.l #imm,rd * extu.w rd * mov.l rs,rd * extu.l rd * mov.l @rs,rd inc rs * mov.l @(disp:16,rs),rd * inc.w #imm,rd * mov.l @(disp:24,rs),rd * inc.l #imm,rd * mov.l @rs+,rd jmp @rs * mov.l @abs:16,rd jmp abs * mov.l @abs:24,rd jmp @@abs:8 * mov.l rs,@rd jsr @rs * mov.l rs,@(disp:16,rd) jsr abs * mov.l rs,@(disp:24,rd) jsr @@abs:8 * mov.l rs,@-rd ldc #imm,ccr * mov.l rs,@abs:16 ldc rs,ccr * mov.l rs,@abs:24 * ldc @abs:16,ccr movfpe @abs:16,rd * ldc @abs:24,ccr movtpe rs,@abs:16 * ldc @(disp:16,rs),ccr mulxu.b rs,rd * ldc @(disp:24,rs),ccr * mulxu.w rs,rd * ldc @rs+,ccr * mulxs.b rs,rd * ldc @rs,ccr * mulxs.w rs,rd * mov.b @(disp:24,rs),rd neg.b rs * mov.b rs,@(disp:24,rd) * neg.w rs mov.b @abs:16,rd * neg.l rs mov.b rs,rd nop mov.b @abs:8,rd not.b rs mov.b rs,@abs:8 * not.w rs mov.b rs,rd * not.l rs mov.b #imm,rd or.b #imm,rd mov.b @rs,rd or.b rs,rd mov.b @(disp:16,rs),rd * or.w #imm,rd mov.b @rs+,rd * or.w rs,rd mov.b @abs:8,rd * or.l #imm,rd mov.b rs,@rd * or.l rs,rd mov.b rs,@(disp:16,rd) orc #imm,ccr mov.b rs,@-rd pop.w rs mov.b rs,@abs:8 * pop.l rs mov.w rs,@rd push.w rs * mov.w @(disp:24,rs),rd * push.l rs * mov.w rs,@(disp:24,rd) rotl.b rs * mov.w @abs:24,rd * rotl.w rs * mov.w rs,@abs:24 * rotl.l rs mov.w rs,rd rotr.b rs mov.w #imm,rd * rotr.w rs mov.w @rs,rd * rotr.l rs mov.w @(disp:16,rs),rd rotxl.b rs mov.w @rs+,rd * rotxl.w rs mov.w @abs:16,rd * rotxl.l rs mov.w rs,@(disp:16,rd) rotxr.b rs mov.w rs,@-rd * rotxr.w rs * rotxr.l rs * stc ccr,@(disp:24,rd) bpt * stc ccr,@-rd rte * stc ccr,@abs:16 rts * stc ccr,@abs:24 shal.b rs sub.b rs,rd * shal.w rs sub.w rs,rd * shal.l rs * sub.w #imm,rd shar.b rs * sub.l rs,rd * shar.w rs * sub.l #imm,rd * shar.l rs subs #imm,rd shll.b rs subx #imm,rd * shll.w rs subx rs,rd * shll.l rs * trapa #imm shlr.b rs xor #imm,rd * shlr.w rs xor rs,rd * shlr.l rs * xor.w #imm,rd sleep * xor.w rs,rd stc ccr,rd * xor.l #imm,rd * stc ccr,@rs * xor.l rs,rd * stc ccr,@(disp:16,rd) xorc #imm,ccr

Four H8/300 instructions (add, cmp, mov, sub) are defined with variants using the suffixes `.b', `.w', and `.l' to specify the size of a memory operand. as supports these suffixes, but does not require them; since one of the operands is always a register, as can deduce the correct size.

For example, since r0 refers to a 16-bit register,

mov r0,@foo is equivalent to mov.w r0,@foo

If you use the size suffixes, as issues a warning when the suffix and the register size do not match.

8.7 H8/500 Dependent Features

8.7.1 Options
8.7.2 Syntax
8.7.3 Floating Point
8.7.4 H8/500 Machine Directives
8.7.5 Opcodes

8.7.1 Options

as has no additional command-line options for the Hitachi H8/500 family.

8.7.2 Syntax

8.7.2.1 Special Characters
8.7.2.2 Register Names
8.7.2.3 Addressing Modes

8.7.2.1 Special Characters

`!' is the line comment character.

`;' can be used instead of a newline to separate statements.

Since `$' has no special meaning, you may use it in symbol names.

8.7.2.2 Register Names

You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', `r6', and `r7' to refer to the H8/500 registers.

The H8/500 also has these control registers:

cp

code pointer

dp

data pointer

bp

base pointer

tp

stack top pointer

ep

extra pointer

sr

status register

ccr

condition code register

All registers are 16 bits long. To represent 32 bit numbers, use two adjacent registers; for distant memory addresses, use one of the segment pointers (cp for the program counter; dp for r0--r3; ep for r4 and r5; and tp for r6 and r7.

8.7.2.3 Addressing Modes

as understands the following addressing modes for the H8/500:

Rn

Register direct

@Rn

Register indirect

@(d:8, Rn)

Register indirect with 8 bit signed displacement

@(d:16, Rn)

Register indirect with 16 bit signed displacement

@-Rn

Register indirect with pre-decrement

@Rn+

Register indirect with post-increment

@aa:8

8 bit absolute address

@aa:16

16 bit absolute address

#xx:8

8 bit immediate

#xx:16

16 bit immediate

8.7.3 Floating Point

The H8/500 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

8.7.4 H8/500 Machine Directives

as has no machine-dependent directives for the H8/500. However, on this platform the `.int' and `.word' directives generate 16-bit numbers.

8.7.5 Opcodes

For detailed information on the H8/500 machine instruction set, see H8/500 Series Programming Manual (Hitachi M21T001).

as implements all the standard H8/500 opcodes. No additional pseudo-instructions are needed on this family.

The following table summarizes H8/500 opcodes and their operands:

Legend: abs8 8-bit absolute address abs16 16-bit absolute address abs24 24-bit absolute address crb ccr, br, ep, dp, tp, dp disp8 8-bit displacement ea rn, @rn, @(d:8, rn), @(d:16, rn), @-rn, @rn+, @aa:8, @aa:16, #xx:8, #xx:16 ea_mem @rn, @(d:8, rn), @(d:16, rn), @-rn, @rn+, @aa:8, @aa:16 ea_noimm rn, @rn, @(d:8, rn), @(d:16, rn), @-rn, @rn+, @aa:8, @aa:16 fp r6 imm4 4-bit immediate data imm8 8-bit immediate data imm16 16-bit immediate data pcrel8 8-bit offset from program counter pcrel16 16-bit offset from program counter qim -2, -1, 1, 2 rd any register rs a register distinct from rd rlist comma-separated list of registers in parentheses; register ranges rd-rs are allowed sp stack pointer (r7) sr status register sz size; `.b' or `.w'. If omitted, default `.w' ldc[.b] ea,crb bcc[.w] pcrel16 ldc[.w] ea,sr bcc[.b] pcrel8 add[:q] sz qim,ea_noimm bhs[.w] pcrel16 add[:g] sz ea,rd bhs[.b] pcrel8 adds sz ea,rd bcs[.w] pcrel16 addx sz ea,rd bcs[.b] pcrel8 and sz ea,rd blo[.w] pcrel16 andc[.b] imm8,crb blo[.b] pcrel8 andc[.w] imm16,sr bne[.w] pcrel16 bpt bne[.b] pcrel8 bra[.w] pcrel16 beq[.w] pcrel16 bra[.b] pcrel8 beq[.b] pcrel8 bt[.w] pcrel16 bvc[.w] pcrel16 bt[.b] pcrel8 bvc[.b] pcrel8 brn[.w] pcrel16 bvs[.w] pcrel16 brn[.b] pcrel8 bvs[.b] pcrel8 bf[.w] pcrel16 bpl[.w] pcrel16 bf[.b] pcrel8 bpl[.b] pcrel8 bhi[.w] pcrel16 bmi[.w] pcrel16 bhi[.b] pcrel8 bmi[.b] pcrel8 bls[.w] pcrel16 bge[.w] pcrel16 bls[.b] pcrel8 bge[.b] pcrel8 blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem bgt[.w] pcrel16 movfpe[.b] ea,rd bgt[.b] pcrel8 movtpe[.b] rs,ea_noimm ble[.w] pcrel16 mulxu sz ea,rd ble[.b] pcrel8 neg sz ea bclr sz imm4,ea_noimm nop bclr sz rs,ea_noimm not sz ea bnot sz imm4,ea_noimm or sz ea,rd bnot sz rs,ea_noimm orc[.b] imm8,crb bset sz imm4,ea_noimm orc[.w] imm16,sr bset sz rs,ea_noimm pjmp abs24 bsr[.b] pcrel8 pjmp @rd bsr[.w] pcrel16 pjsr abs24 btst sz imm4,ea_noimm pjsr @rd btst sz rs,ea_noimm prtd imm8 clr sz ea prtd imm16 cmp[:e][.b] imm8,rd prts cmp[:i][.w] imm16,rd rotl sz ea cmp[:g].b imm8,ea_noimm rotr sz ea cmp[:g][.w] imm16,ea_noimm rotxl sz ea Cmp[:g] sz ea,rd rotxr sz ea dadd rs,rd rtd imm8 divxu sz ea,rd rtd imm16 dsub rs,rd rts exts[.b] rd scb/f rs,pcrel8 extu[.b] rd scb/ne rs,pcrel8 jmp @rd scb/eq rs,pcrel8 jmp @(imm8,rd) shal sz ea jmp @(imm16,rd) shar sz ea jmp abs16 shll sz ea jsr @rd shlr sz ea jsr @(imm8,rd) sleep jsr @(imm16,rd) stc[.b] crb,ea_noimm jsr abs16 stc[.w] sr,ea_noimm ldm @sp+,(rlist) stm (rlist),@-sp link fp,imm8 sub sz ea,rd link fp,imm16 subs sz ea,rd mov[:e][.b] imm8,rd subx sz ea,rd mov[:i][.w] imm16,rd swap[.b] rd mov[:l][.w] abs8,rd tas[.b] ea mov[:l].b abs8,rd trapa imm4 mov[:s][.w] rs,abs8 trap/vs mov[:s].b rs,abs8 tst sz ea mov[:f][.w] @(disp8,fp),rd unlk fp mov[:f][.w] rs,@(disp8,fp) xch[.w] rs,rd mov[:f].b @(disp8,fp),rd xor sz ea,rd mov[:f].b rs,@(disp8,fp) xorc.b imm8,crb mov[:g] sz rs,ea_mem xorc.w imm16,sr mov[:g] sz ea,rd

8.8 HPPA Dependent Features

8.8.1 Notes
8.8.2 Options
8.8.3 Syntax
8.8.4 Floating Point
8.8.5 HPPA Assembler Directives		HPPA Machine Directives
8.8.6 Opcodes

8.8.1 Notes

The format of the debugging sections has changed since the original as port (version 1.3X) was released; therefore, you must rebuild all HPPA objects and libraries with the new assembler so that you can debug the final executable.

The HPPA as port generates a small subset of the relocations available in the SOM and ELF object file formats. Additional relocation support will be added as it becomes necessary.

8.8.2 Options

8.8.3 Syntax

First, a colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

Some obscure expression parsing problems may affect hand written code which uses the spop instructions, or code which makes significant use of the ! line separator.

as is much less forgiving about missing arguments and other similar oversights than the HP assembler. as notifies you of missing arguments as syntax errors; this is regarded as a feature, not a bug.

Finally, as allows you to use an external symbol without explicitly importing the symbol. Warning: in the future this will be an error for HPPA targets.

Special characters for HPPA targets include:

`;' is the line comment character.

`!' can be used instead of a newline to separate statements.

Since `$' has no special meaning, you may use it in symbol names.

8.8.4 Floating Point

8.8.5 HPPA Assembler Directives

as for the HPPA supports many additional directives for compatibility with the native assembler. This section describes them only briefly. For detailed information on HPPA-specific assembler directives, see HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001).

as does not support the following assembler directives described in the HP manual:

.endm .liston .enter .locct .leave .macro .listoff

Beyond those implemented for compatibility, as supports one additional assembler directive for the HPPA: .param. It conveys register argument locations for static functions. Its syntax closely follows the .export directive.

These are the additional directives in as for the HPPA:

.block n

.blockz n

Reserve n bytes of storage, and initialize them to zero.

.call

Mark the beginning of a procedure call. Only the special case with no arguments is allowed.

.callinfo [ param=value, ... ] [ flag, ... ]

Specify a number of parameters and flags that define the environment for a procedure.

param may be any of `frame' (frame size), `entry_gr' (end of general register range), `entry_fr' (end of float register range), `entry_sr' (end of space register range).

The values for flag are `calls' or `caller' (proc has subroutines), `no_calls' (proc does not call subroutines), `save_rp' (preserve return pointer), `save_sp' (proc preserves stack pointer), `no_unwind' (do not unwind this proc), `hpux_int' (proc is interrupt routine).

.code

Assemble into the standard section called `$TEXT$', subsection `$CODE$'.

.copyright "string"

In the SOM object format, insert string into the object code, marked as a copyright string.

.copyright "string"

In the ELF object format, insert string into the object code, marked as a version string.

.enter

Not yet supported; the assembler rejects programs containing this directive.

.entry

Mark the beginning of a procedure.

.exit

Mark the end of a procedure.

.export name [ ,typ ] [ ,param=r ]

Make a procedure name available to callers. typ, if present, must be one of `absolute', `code' (ELF only, not SOM), `data', `entry', `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'.

param, if present, provides either relocation information for the procedure arguments and result, or a privilege level. param may be `argwn' (where n ranges from 0 to 3, and indicates one of four one-word arguments); `rtnval' (the procedure's result); or `priv_lev' (privilege level). For arguments or the result, r specifies how to relocate, and must be one of `no' (not relocatable), `gr' (argument is in general register), `fr' (in floating point register), or `fu' (upper half of float register). For `priv_lev', r is an integer.

.half n

Define a two-byte integer constant n; synonym for the portable as directive .short.

.import name [ ,typ ]

Converse of .export; make a procedure available to call. The arguments use the same conventions as the first two arguments for .export.

.label name

Define name as a label for the current assembly location.

.leave

Not yet supported; the assembler rejects programs containing this directive.

.origin lc

Advance location counter to lc. Synonym for the portable directive .org.

.param name [ ,typ ] [ ,param=r ]

Similar to .export, but used for static procedures.

.proc

Use preceding the first statement of a procedure.

.procend

Use following the last statement of a procedure.

label .reg expr

Synonym for .equ; define label with the absolute expression expr as its value.

.space secname [ ,params ]

Switch to section secname, creating a new section by that name if necessary. You may only use params when creating a new section, not when switching to an existing one. secname may identify a section by number rather than by name.

If specified, the list params declares attributes of the section, identified by keywords. The keywords recognized are `spnum=exp' (identify this section by the number exp, an absolute expression), `sort=exp' (order sections according to this sort key when linking; exp is an absolute expression), `unloadable' (section contains no loadable data), `notdefined' (this section defined elsewhere), and `private' (data in this section not available to other programs).

.spnum secnam

Allocate four bytes of storage, and initialize them with the section number of the section named secnam. (You can define the section number with the HPPA .space directive.)

.string "str"

Copy the characters in the string str to the object file. See section 3.6.1.1 Strings, for information on escape sequences you can use in as strings.

Warning! The HPPA version of .string differs from the usual as definition: it does not write a zero byte after copying str.

.stringz "str"

Like .string, but appends a zero byte after copying str to object file.

.subspa name [ ,params ]

.nsubspa name [ ,params ]

Similar to .space, but selects a subsection name within the current section. You may only specify params when you create a subsection (in the first instance of .subspa for this name).

If specified, the list params declares attributes of the subsection, identified by keywords. The keywords recognized are `quad=expr' ("quadrant" for this subsection), `align=expr' (alignment for beginning of this subsection; a power of two), `access=expr' (value for "access rights" field), `sort=expr' (sorting order for this subspace in link), `code_only' (subsection contains only code), `unloadable' (subsection cannot be loaded into memory), `common' (subsection is common block), `dup_comm' (initialized data may have duplicate names), or `zero' (subsection is all zeros, do not write in object file).

.nsubspa always creates a new subspace with the given name, even if one with the same name already exists.

.version "str"

Write str as version identifier in object code.

8.8.6 Opcodes

8.9 ESA/390 Dependent Features

8.9.1 Notes
8.9.2 Options
8.9.3 Syntax
8.9.4 Floating Point
8.9.5 ESA/390 Assembler Directives		ESA/390 Machine Directives
8.9.6 Opcodes

8.9.1 Notes

When used with the GNU CC compiler, the ESA/390 as will produce correct, fully relocated, functional binaries, and has been used to compile and execute large projects. However, many aspects should still be considered experimental; these include shared library support, dynamically loadable objects, and any relocation other than the 31-bit relocation.

8.9.2 Options

8.9.3 Syntax

A leading dot in front of directives is optional, and the case of directives is ignored; thus for example, .using and USING have the same effect.

A colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

`#' is the line comment character.

`;' can be used instead of a newline to separate statements.

Since `$' has no special meaning, you may use it in symbol names.

Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6. By using thesse symbolic names, as can detect simple syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base for r3 and rpgt or r.pgt for r4.

`*' is the current location counter. Unlike `.' it is always relative to the last USING directive. Note that this means that expressions cannot use multiplication, as any occurence of `*' will be interpreted as a location counter.

All labels are relative to the last USING. Thus, branches to a label always imply the use of base+displacement.

Many of the usual forms of address constants / address literals are supported. Thus,

.using *,r3 L r15,=A(some_routine) LM r6,r7,=V(some_longlong_extern) A r1,=F'12' AH r0,=H'42' ME r6,=E'3.1416' MD r6,=D'3.14159265358979' O r6,=XL4'cacad0d0' .ltorg

should all behave as expected: that is, an entry in the literal pool will be created (or reused if it already exists), and the instruction operands will be the displacement into the literal pool using the current base register (as last declared with the .using directive).

8.9.4 Floating Point

8.9.5 ESA/390 Assembler Directives

as for the ESA/390 supports all of the standard ELF/SVR4 assembler directives that are documented in the main part of this documentation. Several additional directives are supported in order to implement the ESA/390 addressing model. The most important of these are .using and .ltorg

These are the additional directives in as for the ESA/390:

.dc

A small subset of the usual DC directive is supported.

.drop regno

Stop using regno as the base register. The regno must have been previously declared with a .using directive in the same section as the current section.

.ebcdic string

Emit the EBCDIC equivalent of the indicated string. The emitted string will be null terminated. Note that the directives .string etc. emit ascii strings by default.

EQU

The standard HLASM-style EQU directive is not supported; however, the standard as directive .equ can be used to the same effect.

.ltorg

Dump the literal pool accumulated so far; begin a new literal pool. The literal pool will be written in the current section; in order to generate correct assembly, a .using must have been previously specified in the same section.

.using expr,regno

Use regno as the base register for all subsequent RX, RS, and SS form instructions. The expr will be evaluated to obtain the base address; usually, expr will merely be `*'.

This assembler allows two .using directives to be simultaneously outstanding, one in the .text section, and one in another section (typically, the .data section). This feature allows dynamically loaded objects to be implemented in a relatively straightforward way. A .using directive must always be specified in the .text section; this will specify the base register that will be used for branches in the .text section. A second .using may be specified in another section; this will specify the base register that is used for non-label address literals. When a second .using is specified, then the subsequent .ltorg must be put in the same section; otherwise an error will result.

Thus, for example, the following code uses r3 to address branch targets and r4 to address the literal pool, which has been written to the .data section. The is, the constants =A(some_routine), =H'42' and =E'3.1416' will all appear in the .data section.

.data .using LITPOOL,r4 .text BASR r3,0 .using *,r3 B START .long LITPOOL START: L r4,4(,r3) L r15,=A(some_routine) LTR r15,r15 BNE LABEL AH r0,=H'42' LABEL: ME r6,=E'3.1416' .data LITPOOL: .ltorg

Note that this dual-.using directive semantics extends and is not compatible with HLASM semantics. Note that this assembler directive does not support the full range of HLASM semantics.

8.9.6 Opcodes

8.10 80386 Dependent Features

8.10.1 Options
8.10.2 AT&T Syntax versus Intel Syntax
8.10.3 Instruction Naming
8.10.4 Register Naming
8.10.5 Instruction Prefixes
8.10.6 Memory References
8.10.7 Handling of Jump Instructions
8.10.8 Floating Point
8.10.9 Intel's MMX and AMD's 3DNow! SIMD Operations
8.10.10 Writing 16-bit Code
8.10.11 AT&T Syntax bugs
8.10.12 Notes

8.10.1 Options

The 80386 has no machine dependent options.

8.10.2 AT&T Syntax versus Intel Syntax

In order to maintain compatibility with the output of gcc, as supports AT&T System V/386 assembler syntax. This is quite different from Intel syntax. We mention these differences because almost all 80386 documents use Intel syntax. Notable differences between the two syntaxes are:

• AT&T immediate operands are preceded by `$'; Intel immediate operands are undelimited (Intel `push 4' is AT&T `pushl $4'). AT&T register operands are preceded by `%'; Intel register operands are undelimited. AT&T absolute (as opposed to PC relative) jump/call operands are prefixed by `*'; they are undelimited in Intel syntax.

• AT&T and Intel syntax use the opposite order for source and destination operands. Intel `add eax, 4' is `addl $4, %eax'. The `source, dest' convention is maintained for compatibility with previous Unix assemblers. Note that instructions with more than one source operand, such as the `enter' instruction, do not have reversed order. section 8.10.11 AT&T Syntax bugs.

• In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic. Mnemonic suffixes of `b', `w', and `l' specify byte (8-bit), word (16-bit), and long (32-bit) memory references. Intel syntax accomplishes this by prefixing memory operands (not the instruction mnemonics) with `byte ptr', `word ptr', and `dword ptr'. Thus, Intel `mov al, byte ptr foo' is `movb foo, %al' in AT&T syntax.

• Immediate form long jumps and calls are `lcall/ljmp $section, $offset' in AT&T syntax; the Intel syntax is `call/jmp far section:offset'. Also, the far return instruction is `lret $stack-adjust' in AT&T syntax; Intel syntax is `ret far stack-adjust'.

• The AT&T assembler does not provide support for multiple section programs. Unix style systems expect all programs to be single sections.

8.10.3 Instruction Naming

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands. The letters `b', `w', and `l' specify byte, word, and long operands. If no suffix is specified by an instruction then as tries to fill in the missing suffix based on the destination register operand (the last one by convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx'; also, `mov $1, %bx' is equivalent to `movw $1, %bx'. Note that this is incompatible with the AT&T Unix assembler which assumes that a missing mnemonic suffix implies long operand size. (This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix.)

Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend from and a size to zero extend to. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend and zero extend are `movs...' and `movz...' in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, `movsbl %al, %edx' is AT&T syntax for "move sign extend from %al to %edx." Possible suffixes, thus, are `bl' (from byte to long), `bw' (from byte to word), and `wl' (from word to long).

The Intel-syntax conversion instructions

• `cbw' -- sign-extend byte in `%al' to word in `%ax',

• `cwde' -- sign-extend word in `%ax' to long in `%eax',

• `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax',

• `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax',

are called `cbtw', `cwtl', `cwtd', and `cltd' in AT&T naming. as accepts either naming for these instructions.

Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax, but are `call far' and `jump far' in Intel convention.

8.10.4 Register Naming

Register operands are always prefixed with `%'. The 80386 registers consist of

• the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp' (the stack pointer).

• the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di', `%si', `%bp', and `%sp'.

• the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl', `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax', `%bx', `%cx', and `%dx')

• the 6 section registers `%cs' (code section), `%ds' (data section), `%ss' (stack section), `%es', `%fs', and `%gs'.

• the 3 processor control registers `%cr0', `%cr2', and `%cr3'.

• the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and `%db7'.

• the 2 test registers `%tr6' and `%tr7'.

• the 8 floating point register stack `%st' or equivalently `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)', `%st(6)', and `%st(7)'.

8.10.5 Instruction Prefixes

Instruction prefixes are used to modify the following instruction. They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to change operand and address sizes. (Most instructions that normally operate on 32-bit operands will use 16-bit operands if the instruction has an "operand size" prefix.) Instruction prefixes are best written on the same line as the instruction they act upon. For example, the `scas' (scan string) instruction is repeated with:

repne scas %es:(%edi),%al

You may also place prefixes on the lines immediately preceding the instruction, but this circumvents checks that as does with prefixes, and will not work with all prefixes.

Here is a list of instruction prefixes:

• Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'. These are automatically added by specifying using the section:memory-operand form for memory references.

• Operand/Address size prefixes `data16' and `addr16' change 32-bit operands/addresses into 16-bit operands/addresses, while `data32' and `addr32' change 16-bit ones (in a .code16 section) into 32-bit operands/addresses. These prefixes must appear on the same line of code as the instruction they modify. For example, in a 16-bit .code16 section, you might write:

  addr32 jmpl *(%ebx)

• The bus lock prefix `lock' inhibits interrupts during execution of the instruction it precedes. (This is only valid with certain instructions; see a 80386 manual for details).

• The wait for coprocessor prefix `wait' waits for the coprocessor to complete the current instruction. This should never be needed for the 80386/80387 combination.

• The `rep', `repe', and `repne' prefixes are added to string instructions to make them repeat `%ecx' times (`%cx' times if the current address size is 16-bits).

8.10.6 Memory References

An Intel syntax indirect memory reference of the form

section:[base + index*scale + disp]

is translated into the AT&T syntax

section:disp(base, index, scale)

where base and index are the optional 32-bit base and index registers, disp is the optional displacement, and scale, taking the values 1, 2, 4, and 8, multiplies index to calculate the address of the operand. If no scale is specified, scale is taken to be 1. section specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register defaults). Note that section overrides in AT&T syntax must be preceded by a `%'. If you specify a section override which coincides with the default section register, as does not output any section register override prefixes to assemble the given instruction. Thus, section overrides can be specified to emphasize which section register is used for a given memory operand.

Here are some examples of Intel and AT&T style memory references:

AT&T: `-4(%ebp)', Intel: `[ebp - 4]'

base is `%ebp'; disp is `-4'. section is missing, and the default section is used (`%ss' for addressing with `%ebp' as the base register). index, scale are both missing.

AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]'

index is `%eax' (scaled by a scale 4); disp is `foo'. All other fields are missing. The section register here defaults to `%ds'.

AT&T: `foo(,1)'; Intel `[foo]'

This uses the value pointed to by `foo' as a memory operand. Note that base and index are both missing, but there is only one `,'. This is a syntactic exception.

AT&T: `%gs:foo'; Intel `gs:foo'

This selects the contents of the variable `foo' with section register section being `%gs'.

Absolute (as opposed to PC relative) call and jump operands must be prefixed with `*'. If no `*' is specified, as always chooses PC relative addressing for jump/call labels.

Any instruction that has a memory operand, but no register operand, must specify its size (byte, word, or long) with an instruction mnemonic suffix (`b', `w', or `l', respectively).

8.10.7 Handling of Jump Instructions

Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long (32-bit) displacement is used. We do not support word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction with the `data16' instruction prefix), since the 80386 insists upon masking `%eip' to 16 bits after the word displacement is added.

Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz' and `loopne' instructions only come in byte displacements, so that if you use these instructions (gcc does not use them) you may get an error message (and incorrect code). The AT&T 80386 assembler tries to get around this problem by expanding `jcxz foo' to

jcxz cx_zero jmp cx_nonzero cx_zero: jmp foo cx_nonzero:

8.10.8 Floating Point

All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each supported type has an instruction mnemonic suffix and a constructor associated with it. Instruction mnemonic suffixes specify the operand's data type. Constructors build these data types into memory.

• Floating point constructors are `.float' or `.single', `.double', and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for 80-bit (ten byte) real. The 80387 only supports this format via the `fldt' (load 80-bit real to stack top) and `fstpt' (store 80-bit real and pop stack) instructions.

• Integer constructors are `.word', `.long' or `.int', and `.quad' for the 16-, 32-, and 64-bit integer formats. The corresponding instruction mnemonic suffixes are `s' (single), `l' (long), and `q' (quad). As with the 80-bit real format, the 64-bit `q' format is only present in the `fildq' (load quad integer to stack top) and `fistpq' (store quad integer and pop stack) instructions.

Register to register operations should not use instruction mnemonic suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as if you wrote `fst %st, %st(1)', since all register to register operations use 80-bit floating point operands. (Contrast this with `fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating point format, then stores the result in the 4 byte location `mem')

8.10.9 Intel's MMX and AMD's 3DNow! SIMD Operations

as supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future.

Currently, as does not support Intel's floating point SIMD, Katmai (KNI).

The eight 64-bit MMX operands, also used by 3DNow!, are called `%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit floating point values. The MMX registers cannot be used at the same time as the floating point stack.

See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax.

8.10.10 Writing 16-bit Code

While as normally writes only "pure" 32-bit i386 code, it also supports writing code to run in real mode or in 16-bit protected mode code segments. To do this, put a `.code16' or `.code16gcc' directive before the assembly language instructions to be run in 16-bit mode. You can switch as back to writing normal 32-bit code with the `.code32' directive.

`.code16gcc' provides experimental support for generating 16-bit code from gcc, and differs from `.code16' in that `call', `ret', `enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf' instructions default to 32-bit size. This is so that the stack pointer is manipulated in the same way over function calls, allowing access to function parameters at the same stack offsets as in 32-bit mode. `.code16gcc' also automatically adds address size prefixes where necessary to use the 32-bit addressing modes that gcc generates.

The code which as generates in 16-bit mode will not necessarily run on a 16-bit pre-80386 processor. To write code that runs on such a processor, you must refrain from using any 32-bit constructs which require as to output address or operand size prefixes.

Note that writing 16-bit code instructions by explicitly specifying a prefix or an instruction mnemonic suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment. In a 32-bit code section, the following code generates the machine opcode bytes `66 6a 04', which pushes the value `4' onto the stack, decrementing `%esp' by 2.

pushw $4

The same code in a 16-bit code section would generate the machine opcode bytes `6a 04' (ie. without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section.

8.10.11 AT&T Syntax bugs

The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc and possibly many other programs use this reversed syntax, so we're stuck with it.

For example

fsub %st,%st(3)

results in `%st(3)' being updated to `%st - %st(3)' rather than the expected `%st(3) - %st'. This happens with all the non-commutative arithmetic floating point operations with two register operands where the source register is `%st' and the destination register is `%st(i)'.

8.10.12 Notes

There is some trickery concerning the `mul' and `imul' instructions that deserves mention. The 16-, 32-, and 64-bit expanding multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') can be output only in the one operand form. Thus, `imul %ebx, %eax' does not select the expanding multiply; the expanding multiply would clobber the `%edx' register, and this would confuse gcc output. Use `imul %ebx' to get the 64-bit product in `%edx:%eax'.

We have added a two operand form of `imul' when the first operand is an immediate mode expression and the second operand is a register. This is just a shorthand, so that, multiplying `%eax' by 69, for example, can be done with `imul $69, %eax' rather than `imul $69, %eax, %eax'.

8.11 Intel 80960 Dependent Features

8.11.1 i960 Command-line Options
8.11.2 Floating Point
8.11.3 i960 Machine Directives
8.11.4 i960 Opcodes

8.11.1 i960 Command-line Options

-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC

Select the 80960 architecture. Instructions or features not supported by the selected architecture cause fatal errors.

`-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. Synonyms are provided for compatibility with other tools.

If you do not specify any of these options, as generates code for any instruction or feature that is supported by some version of the 960 (even if this means mixing architectures!). In principle, as attempts to deduce the minimal sufficient processor type if none is specified; depending on the object code format, the processor type may be recorded in the object file. If it is critical that the as output match a specific architecture, specify that architecture explicitly.

-b

Add code to collect information about conditional branches taken, for later optimization using branch prediction bits. (The conditional branch instructions have branch prediction bits in the CA, CB, and CC architectures.) If BR represents a conditional branch instruction, the following represents the code generated by the assembler when `-b' is specified:

call increment routine .word 0 # pre-counter Label: BR call increment routine .word 0 # post-counter

The counter following a branch records the number of times that branch was not taken; the differenc between the two counters is the number of times the branch was taken.

A table of every such Label is also generated, so that the external postprocessor gbr960 (supplied by Intel) can locate all the counters. This table is always labelled `__BRANCH_TABLE__'; this is a local symbol to permit collecting statistics for many separate object files. The table is word aligned, and begins with a two-word header. The first word, initialized to 0, is used in maintaining linked lists of branch tables. The second word is a count of the number of entries in the table, which follow immediately: each is a word, pointing to one of the labels illustrated above.

+------------+------------+------------+ ... +------------+ | | | | | | | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | | | | | | | +------------+------------+------------+ ... +------------+ __BRANCH_TABLE__ layout

The first word of the header is used to locate multiple branch tables, since each object file may contain one. Normally the links are maintained with a call to an initialization routine, placed at the beginning of each function in the file. The GNU C compiler generates these calls automatically when you give it a `-b' option. For further details, see the documentation of `gbr960'.

-no-relax

Normally, Compare-and-Branch instructions with targets that require displacements greater than 13 bits (or that have external targets) are replaced with the corresponding compare (or `chkbit') and branch instructions. You can use the `-no-relax' option to specify that as should generate errors instead, if the target displacement is larger than 13 bits.

This option does not affect the Compare-and-Jump instructions; the code emitted for them is always adjusted when necessary (depending on displacement size), regardless of whether you use `-no-relax'.

8.11.2 Floating Point

as generates IEEE floating-point numbers for the directives `.float', `.double', `.extended', and `.single'.

8.11.3 i960 Machine Directives

.bss symbol, length, align

Reserve length bytes in the bss section for a local symbol, aligned to the power of two specified by align. length and align must be positive absolute expressions. This directive differs from `.lcomm' only in that it permits you to specify an alignment. See section 7.39 .lcomm symbol , length.

.extended flonums

.extended expects zero or more flonums, separated by commas; for each flonum, `.extended' emits an IEEE extended-format (80-bit) floating-point number.

.leafproc call-lab, bal-lab

You can use the `.leafproc' directive in conjunction with the optimized callj instruction to enable faster calls of leaf procedures. If a procedure is known to call no other procedures, you may define an entry point that skips procedure prolog code (and that does not depend on system-supplied saved context), and declare it as the bal-lab using `.leafproc'. If the procedure also has an entry point that goes through the normal prolog, you can specify that entry point as call-lab.

A `.leafproc' declaration is meant for use in conjunction with the optimized call instruction `callj'; the directive records the data needed later to choose between converting the `callj' into a bal or a call.

call-lab is optional; if only one argument is present, or if the two arguments are identical, the single argument is assumed to be the bal entry point.

.sysproc name, index

The `.sysproc' directive defines a name for a system procedure. After you define it using `.sysproc', you can use name to refer to the system procedure identified by index when calling procedures with the optimized call instruction `callj'.

Both arguments are required; index must be between 0 and 31 (inclusive).

8.11.4 i960 Opcodes

All Intel 960 machine instructions are supported; see section 8.11.1 i960 Command-line Options for a discussion of selecting the instruction subset for a particular 960 architecture.

Some opcodes are processed beyond simply emitting a single corresponding instruction: `callj', and Compare-and-Branch or Compare-and-Jump instructions with target displacements larger than 13 bits.

8.11.4.1 callj
8.11.4.2 Compare-and-Branch

8.11.4.1 callj

You can write callj to have the assembler or the linker determine the most appropriate form of subroutine call: `call', `bal', or `calls'. If the assembly source contains enough information--a `.leafproc' or `.sysproc' directive defining the operand--then as translates the callj; if not, it simply emits the callj, leaving it for the linker to resolve.

8.11.4.2 Compare-and-Branch

The 960 architectures provide combined Compare-and-Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself. However, if you specify a branch target far enough away that its address won't fit in 13 bits, the assembler can either issue an error, or convert your Compare-and-Branch instruction into separate instructions to do the compare and the branch.

Whether as gives an error or expands the instruction depends on two choices you can make: whether you use the `-no-relax' option, and whether you use a "Compare and Branch" instruction or a "Compare and Jump" instruction. The "Jump" instructions are always expanded if necessary; the "Branch" instructions are expanded when necessary unless you specify -no-relax---in which case as gives an error instead.

These are the Compare-and-Branch instructions, their "Jump" variants, and the instruction pairs they may expand into:

Compare and Branch Jump Expanded to ------ ------ ------------ bbc chkbit; bno bbs chkbit; bo cmpibe cmpije cmpi; be cmpibg cmpijg cmpi; bg cmpibge cmpijge cmpi; bge cmpibl cmpijl cmpi; bl cmpible cmpijle cmpi; ble cmpibno cmpijno cmpi; bno cmpibne cmpijne cmpi; bne cmpibo cmpijo cmpi; bo cmpobe cmpoje cmpo; be cmpobg cmpojg cmpo; bg cmpobge cmpojge cmpo; bge cmpobl cmpojl cmpo; bl cmpoble cmpojle cmpo; ble cmpobne cmpojne cmpo; bne

8.12 M680x0 Dependent Features

8.12.1 M680x0 Options
8.12.2 Syntax
8.12.3 Motorola Syntax
8.12.4 Floating Point
8.12.5 680x0 Machine Directives
8.12.6 Opcodes

8.12.1 M680x0 Options

The Motorola 680x0 version of as has a few machine dependent options.

You can use the `-l' option to shorten the size of references to undefined symbols. If you do not use the `-l' option, references to undefined symbols are wide enough for a full long (32 bits). (Since as cannot know where these symbols end up, as can only allocate space for the linker to fill in later. Since as does not know how far away these symbols are, it allocates as much space as it can.) If you use this option, the references are only one word wide (16 bits). This may be useful if you want the object file to be as small as possible, and you know that the relevant symbols are always less than 17 bits away.

For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user variables, the assembler requires a `%' before any use of a register name. This is intended to let the assembler distinguish between C variables and functions named `a0' through `a7', and so on. The `%' is always accepted, but is not required for certain configurations, notably `sun3'. The `--register-prefix-optional' option may be used to permit omitting the `%' even for configurations for which it is normally required. If this is done, it will generally be impossible to refer to C variables and functions with the same names as register names.

Normally the character `|' is treated as a comment character, which means that it can not be used in expressions. The `--bitwise-or' option turns `|' into a normal character. In this mode, you must either use C style comments, or start comments with a `#' character at the beginning of a line.

If you use an addressing mode with a base register without specifying the size, as will normally use the full 32 bit value. For example, the addressing mode `%a0@(%d0)' is equivalent to `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to tell as to default to using the 16 bit value. In this case, `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the `--base-size-default-32' option to restore the default behaviour.

If you use an addressing mode with a displacement, and the value of the displacement is not known, as will normally assume that the value is 32 bits. For example, if the symbol `disp' has not been defined, as will assemble the addressing mode `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use the `--disp-size-default-16' option to tell as to instead assume that the displacement is 16 bits. In this case, as will assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You may use the `--disp-size-default-32' option to restore the default behaviour.

as can assemble code for several different members of the Motorola 680x0 family. The default depends upon how as was configured when it was built; normally, the default is to assemble code for the 68020 microprocessor. The following options may be used to change the default. These options control which instructions and addressing modes are permitted. The members of the 680x0 family are very similar. For detailed information about the differences, see the Motorola manuals.

`-m68000'

`-m68ec000'

`-m68hc000'

`-m68hc001'

`-m68008'

`-m68302'

`-m68306'

`-m68307'

`-m68322'

`-m68356'

Assemble for the 68000. `-m68008', `-m68302', and so on are synonyms for `-m68000', since the chips are the same from the point of view of the assembler.

`-m68010'

Assemble for the 68010.

`-m68020'

`-m68ec020'

Assemble for the 68020. This is normally the default.

`-m68030'

`-m68ec030'

Assemble for the 68030.

`-m68040'

`-m68ec040'

Assemble for the 68040.

`-m68060'

`-m68ec060'

Assemble for the 68060.

`-mcpu32'

`-m68330'

`-m68331'

`-m68332'

`-m68333'

`-m68334'

`-m68336'

`-m68340'

`-m68341'

`-m68349'

`-m68360'

Assemble for the CPU32 family of chips.

`-m5200'

Assemble for the ColdFire family of chips.

`-m68881'

`-m68882'

Assemble 68881 floating point instructions. This is the default for the 68020, 68030, and the CPU32. The 68040 and 68060 always support floating point instructions.

`-mno-68881'

Do not assemble 68881 floating point instructions. This is the default for 68000 and the 68010. The 68040 and 68060 always support floating point instructions, even if this option is used.

`-m68851'

Assemble 68851 MMU instructions. This is the default for the 68020, 68030, and 68060. The 68040 accepts a somewhat different set of MMU instructions; `-m68851' and `-m68040' should not be used together.

`-mno-68851'

Do not assemble 68851 MMU instructions. This is the default for the 68000, 68010, and the CPU32. The 68040 accepts a somewhat different set of MMU instructions.

8.12.2 Syntax

This syntax for the Motorola 680x0 was developed at MIT.

The 680x0 version of as uses instructions names and syntax compatible with the Sun assembler. Intervening periods are ignored; for example, `movl' is equivalent to `mov.l'.

In the following table apc stands for any of the address registers (`%a0' through `%a7'), the program counter (`%pc'), the zero-address relative to the program counter (`%zpc'), a suppressed address register (`%za0' through `%za7'), or it may be omitted entirely. The use of size means one of `w' or `l', and it may be omitted, along with the leading colon, unless a scale is also specified. The use of scale means one of `1', `2', `4', or `8', and it may always be omitted along with the leading colon.

The following addressing modes are understood:

Immediate

`#number'

Data Register

`%d0' through `%d7'

Address Register

`%a0' through `%a7'
`%a7' is also known as `%sp', i.e. the Stack Pointer. %a6 is also known as `%fp', the Frame Pointer.

Address Register Indirect

`%a0@' through `%a7@'

Address Register Postincrement

`%a0@+' through `%a7@+'

Address Register Predecrement

`%a0@-' through `%a7@-'

Indirect Plus Offset

`apc@(number)'

Index

`apc@(number,register:size:scale)'

The number may be omitted.

Postindex

`apc@(number)@(onumber,register:size:scale)'

The onumber or the register, but not both, may be omitted.

Preindex

`apc@(number,register:size:scale)@(onumber)'

The number may be omitted. Omitting the register produces the Postindex addressing mode.

Absolute

`symbol', or `digits', optionally followed by `:b', `:w', or `:l'.

8.12.3 Motorola Syntax

The standard Motorola syntax for this chip differs from the syntax already discussed (see section 8.12.2 Syntax). as can accept Motorola syntax for operands, even if MIT syntax is used for other operands in the same instruction. The two kinds of syntax are fully compatible.

In the following table apc stands for any of the address registers (`%a0' through `%a7'), the program counter (`%pc'), the zero-address relative to the program counter (`%zpc'), or a suppressed address register (`%za0' through `%za7'). The use of size means one of `w' or `l', and it may always be omitted along with the leading dot. The use of scale means one of `1', `2', `4', or `8', and it may always be omitted along with the leading asterisk.

The following additional addressing modes are understood:

Address Register Indirect

`(%a0)' through `(%a7)'
`%a7' is also known as `%sp', i.e. the Stack Pointer. %a6 is also known as `%fp', the Frame Pointer.

Address Register Postincrement

`(%a0)+' through `(%a7)+'

Address Register Predecrement

`-(%a0)' through `-(%a7)'

Indirect Plus Offset

`number(%a0)' through `number(%a7)', or `number(%pc)'.

The number may also appear within the parentheses, as in `(number,%a0)'. When used with the pc, the number may be omitted (with an address register, omitting the number produces Address Register Indirect mode).

Index

`number(apc,register.size*scale)'

The number may be omitted, or it may appear within the parentheses. The apc may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.

Postindex

`([number,apc],register.size*scale,onumber)'

The onumber, or the register, or both, may be omitted. Either the number or the apc may be omitted, but not both.

Preindex

`([number,apc,register.size*scale],onumber)'

The number, or the apc, or the register, or any two of them, may be omitted. The onumber may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.

8.12.4 Floating Point

Packed decimal (P) format floating literals are not supported. Feel free to add the code!

The floating point formats generated by directives are these.

.float

Single precision floating point constants.

.double

Double precision floating point constants.

.extend

.ldouble

Extended precision (long double) floating point constants.

8.12.5 680x0 Machine Directives

In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives.

.data1

This directive is identical to a .data 1 directive.

.data2

This directive is identical to a .data 2 directive.

.even

This directive is a special case of the .align directive; it aligns the output to an even byte boundary.

.skip

This directive is identical to a .space directive.

8.12.6 Opcodes

8.12.6.1 Branch Improvement
8.12.6.2 Special Characters

8.12.6.1 Branch Improvement

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting `j' for `b' at the start of a Motorola mnemonic.

The following table summarizes the pseudo-operations. A * flags cases that are more fully described after the table:

Displacement +------------------------------------------------- | 68020 68000/10 Pseudo-Op |BYTE WORD LONG LONG non-PC relative +------------------------------------------------- jbsr |bsrs bsr bsrl jsr jsr jra |bras bra bral jmp jmp * jXX |bXXs bXX bXXl bNXs;jmpl bNXs;jmp * dbXX |dbXX dbXX dbXX; bra; jmpl * fjXX |fbXXw fbXXw fbXXl fbNXw;jmp XX: condition NX: negative of condition XX

jbsr

jra

These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target.

jXX

Here, `jXX' stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is:

jhi jls jcc jcs jne jeq jvc jvs jpl jmi jge jlt jgt jle

For the cases of non-PC relative displacements and long displacements on the 68000 or 68010, as issues a longer code fragment in terms of NX, the opposite condition to XX. For example, for the non-PC relative case:

jXX foo

gives

bNXs oof jmp foo oof:

dbXX

The full family of pseudo-operations covered here is

dbhi dbls dbcc dbcs dbne dbeq dbvc dbvs dbpl dbmi dbge dblt dbgt dble dbf dbra dbt

Other than for word and byte displacements, when the source reads `dbXX foo', as emits

dbXX oo1 bra oo2 oo1:jmpl foo oo2:

fjXX

This family includes

fjne fjeq fjge fjlt fjgt fjle fjf fjt fjgl fjgle fjnge fjngl fjngle fjngt fjnle fjnlt fjoge fjogl fjogt fjole fjolt fjor fjseq fjsf fjsne fjst fjueq fjuge fjugt fjule fjult fjun

For branch targets that are not PC relative, as emits

fbNX oof jmp foo oof:

when it encounters `fjXX foo'.

8.12.6.2 Special Characters

The immediate character is `#' for Sun compatibility. The line-comment character is `|' (unless the `--bitwise-or' option is used). If a `#' appears at the beginning of a line, it is treated as a comment unless it looks like `# line file', in which case it is treated normally.

8.13 MIPS Dependent Features

GNU as for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through IV. For information about the MIPS instruction set, see MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall). For an overview of MIPS assembly conventions, see "Appendix D: Assembly Language Programming" in the same work.

8.13.1 Assembler options
8.13.2 MIPS ECOFF object code		ECOFF object code
8.13.3 Directives for debugging information
8.13.4 Directives to override the ISA level
8.13.5 Directives for extending MIPS 16 bit instructions
8.13.6 Directive to mark data as an instruction
8.13.7 Directives to save and restore options

8.13.1 Assembler options

The MIPS configurations of GNU as support these special options:

-G num

This option sets the largest size of an object that can be referenced implicitly with the gp register. It is only accepted for targets that use ECOFF format. The default value is 8.

-EB

-EL

Any MIPS configuration of as can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other). Use `-EB' to select big-endian output, and `-EL' for little-endian.

-mips1

-mips2

-mips3

-mips4

Generate code for a particular MIPS Instruction Set Architecture level. `-mips1' corresponds to the R2000 and R3000 processors, `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, and `-mips4' to the R8000 and R10000 processors. You can also switch instruction sets during the assembly; see section 8.13.4 Directives to override the ISA level.

-mgp32

Assume that 32-bit general purpose registers are available. This affects synthetic instructions such as move, which will assemble to a 32-bit or a 64-bit instruction depending on this flag. On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers.

-mgp64

Assume that 64-bit general purpose registers are available. This is provided in the interests of symmetry with -gp32.

-mips16

-no-mips16

Generate code for the MIPS 16 processor. This is equivalent to putting `.set mips16' at the start of the assembly file. `-no-mips16' turns off this option.

-mfix7000

-no-mfix7000

Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.

-m4010

-no-m4010

Generate code for the LSI R4010 chip. This tells the assembler to accept the R4010 specific instructions (`addciu', `ffc', etc.), and to not schedule `nop' instructions around accesses to the `HI' and `LO' registers. `-no-m4010' turns off this option.

-m4650

-no-m4650

Generate code for the MIPS R4650 chip. This tells the assembler to accept the `mad' and `madu' instruction, and to not schedule `nop' instructions around accesses to the `HI' and `LO' registers. `-no-m4650' turns off this option.

-m3900

-no-m3900

-m4100

-no-m4100

For each option `-mnnnn', generate code for the MIPS RNNNN chip. This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards.

-mcpu=cpu

Generate code for a particular MIPS cpu. It is exactly equivalent to `-mcpu', except that there are more value of cpu understood. Valid cpu value are:

2000, 3000, 3900, 4000, 4010, 4100, 4111, 4300, 4400, 4600, 4650, 5000, 6000, 8000, 10000

-nocpp

This option is ignored. It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing. With GNU as, there is no need for `-nocpp', because the GNU assembler itself never runs the C preprocessor.

--trap

--no-break

as automatically macro expands certain division and multiplication instructions to check for overflow and division by zero. This option causes as to generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher.

--break

--no-trap

Generate code to take a break exception rather than a trap exception when an error is detected. This is the default.

8.13.2 MIPS ECOFF object code

Assembling for a MIPS ECOFF target supports some additional sections besides the usual .text, .data and .bss. The additional sections are .rdata, used for read-only data, .sdata, used for small data, and .sbss, used for small common objects.

When assembling for ECOFF, the assembler uses the $gp ($28) register to form the address of a "small object". Any object in the .sdata or .sbss sections is considered "small" in this sense. For external objects, or for objects in the .bss section, you can use the gcc `-G' option to control the size of objects addressed via $gp; the default value is 8, meaning that a reference to any object eight bytes or smaller uses $gp. Passing `-G 0' to as prevents it from using the $gp register on the basis of object size (but the assembler uses $gp for objects in .sdata or sbss in any case). The size of an object in the .bss section is set by the .comm or .lcomm directive that defines it. The size of an external object may be set with the .extern directive. For example, `.extern sym,4' declares that the object at sym is 4 bytes in length, whie leaving sym otherwise undefined.

Using small ECOFF objects requires linker support, and assumes that the $gp register is correctly initialized (normally done automatically by the startup code). MIPS ECOFF assembly code must not modify the $gp register.

8.13.3 Directives for debugging information

MIPS ECOFF as supports several directives used for generating debugging information which are not support by traditional MIPS assemblers. These are .def, .endef, .dim, .file, .scl, .size, .tag, .type, .val, .stabd, .stabn, and .stabs. The debugging information generated by the three .stab directives can only be read by GDB, not by traditional MIPS debuggers (this enhancement is required to fully support C++ debugging). These directives are primarily used by compilers, not assembly language programmers!

8.13.4 Directives to override the ISA level

GNU as supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: .set mipsn. n should be a number from 0 to 4. A value from 1 to 4 makes the assembler accept instructions for the corresponding ISA level, from that point on in the assembly. .set mipsn affects not only which instructions are permitted, but also how certain macros are expanded. .set mips0 restores the ISA level to its original level: either the level you selected with command line options, or the default for your configuration. You can use this feature to permit specific R4000 instructions while assembling in 32 bit mode. Use this directive with care!

The directive `.set mips16' puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor. Use `.set nomips16' to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.

8.13.5 Directives for extending MIPS 16 bit instructions

By default, MIPS 16 instructions are automatically extended to 32 bits when necessary. The directive `.set noautoextend' will turn this off. When `.set noautoextend' is in effect, any 32 bit instruction must be explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The directive `.set autoextend' may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS 16 mode. Traditional MIPS assemblers do not support this directive.

8.13.6 Directive to mark data as an instruction

The .insn directive tells as that the following data is actually instructions. This makes a difference in MIPS 16 mode: when loading the address of a label which precedes instructions, as automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.

8.13.7 Directives to save and restore options

The directives .set push and .set pop may be used to save and restore the current settings for all the options which are controlled by .set. The .set push directive saves the current settings on a stack. The .set pop directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional MIPS assemblers do not support these directives.

8.14 picoJava Dependent Features

8.14.1 Options

8.14.1 Options

as has two addiitional command-line options for the picoJava architecture.

-ml

This option selects little endian data output.

-mb

This option selects big endian data output.

8.15 Hitachi SH Dependent Features

8.15.1 Options
8.15.2 Syntax
8.15.3 Floating Point
8.15.4 SH Machine Directives
8.15.5 Opcodes

8.15.1 Options

as has no additional command-line options for the Hitachi SH family.

8.15.2 Syntax

8.15.2.1 Special Characters
8.15.2.2 Register Names
8.15.2.3 Addressing Modes

8.15.2.1 Special Characters

`!' is the line comment character.

You can use `;' instead of a newline to separate statements.

Since `$' has no special meaning, you may use it in symbol names.

8.15.2.2 Register Names

You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', `r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to refer to the SH registers.

The SH also has these control registers:

pr

procedure register (holds return address)

pc

program counter

mach

macl

high and low multiply accumulator registers

sr

status register

gbr

global base register

vbr

vector base register (for interrupt vectors)

8.15.2.3 Addressing Modes

as understands the following addressing modes for the SH. Rn in the following refers to any of the numbered registers, but not the control registers.

Rn

Register direct

@Rn

Register indirect

@-Rn

Register indirect with pre-decrement

@Rn+

Register indirect with post-increment

@(disp, Rn)

Register indirect with displacement

@(R0, Rn)

Register indexed

@(disp, GBR)

GBR offset

@(R0, GBR)

GBR indexed

addr

@(disp, PC)

PC relative address (for branch or for addressing memory). The as implementation allows you to use the simpler form addr anywhere a PC relative address is called for; the alternate form is supported for compatibility with other assemblers.

#imm

Immediate data

8.15.3 Floating Point

The SH family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

8.15.4 SH Machine Directives

uaword

ualong

as will issue a warning when a misaligned .word or .long directive is used. You may use .uaword or .ualong to indicate that the value is intentionally misaligned.

8.15.5 Opcodes

For detailed information on the SH machine instruction set, see SH-Microcomputer User's Manual (Hitachi Micro Systems, Inc.).

as implements all the standard SH opcodes. No additional pseudo-instructions are needed on this family. Note, however, that because as supports a simpler form of PC-relative addressing, you may simply write (for example)

mov.l bar,r0

where other assemblers might require an explicit displacement to bar from the program counter:

mov.l @(disp, PC)

Here is a summary of SH opcodes:

Legend: Rn a numbered register Rm another numbered register #imm immediate data disp displacement disp8 8-bit displacement disp12 12-bit displacement add #imm,Rn lds.l @Rn+,PR add Rm,Rn mac.w @Rm+,@Rn+ addc Rm,Rn mov #imm,Rn addv Rm,Rn mov Rm,Rn and #imm,R0 mov.b Rm,@(R0,Rn) and Rm,Rn mov.b Rm,@-Rn and.b #imm,@(R0,GBR) mov.b Rm,@Rn bf disp8 mov.b @(disp,Rm),R0 bra disp12 mov.b @(disp,GBR),R0 bsr disp12 mov.b @(R0,Rm),Rn bt disp8 mov.b @Rm+,Rn clrmac mov.b @Rm,Rn clrt mov.b R0,@(disp,Rm) cmp/eq #imm,R0 mov.b R0,@(disp,GBR) cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) cmp/gt Rm,Rn mov.l Rm,@-Rn cmp/hi Rm,Rn mov.l Rm,@Rn cmp/hs Rm,Rn mov.l @(disp,Rn),Rm cmp/pl Rn mov.l @(disp,GBR),R0 cmp/pz Rn mov.l @(disp,PC),Rn cmp/str Rm,Rn mov.l @(R0,Rm),Rn div0s Rm,Rn mov.l @Rm+,Rn div0u mov.l @Rm,Rn div1 Rm,Rn mov.l R0,@(disp,GBR) exts.b Rm,Rn mov.w Rm,@(R0,Rn) exts.w Rm,Rn mov.w Rm,@-Rn extu.b Rm,Rn mov.w Rm,@Rn extu.w Rm,Rn mov.w @(disp,Rm),R0 jmp @Rn mov.w @(disp,GBR),R0 jsr @Rn mov.w @(disp,PC),Rn ldc Rn,GBR mov.w @(R0,Rm),Rn ldc Rn,SR mov.w @Rm+,Rn ldc Rn,VBR mov.w @Rm,Rn ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) ldc.l @Rn+,SR mov.w R0,@(disp,GBR) ldc.l @Rn+,VBR mova @(disp,PC),R0 lds Rn,MACH movt Rn lds Rn,MACL muls Rm,Rn lds Rn,PR mulu Rm,Rn lds.l @Rn+,MACH neg Rm,Rn lds.l @Rn+,MACL negc Rm,Rn nop stc VBR,Rn not Rm,Rn stc.l GBR,@-Rn or #imm,R0 stc.l SR,@-Rn or Rm,Rn stc.l VBR,@-Rn or.b #imm,@(R0,GBR) sts MACH,Rn rotcl Rn sts MACL,Rn rotcr Rn sts PR,Rn rotl Rn sts.l MACH,@-Rn rotr Rn sts.l MACL,@-Rn rte sts.l PR,@-Rn rts sub Rm,Rn sett subc Rm,Rn shal Rn subv Rm,Rn shar Rn swap.b Rm,Rn shll Rn swap.w Rm,Rn shll16 Rn tas.b @Rn shll2 Rn trapa #imm shll8 Rn tst #imm,R0 shlr Rn tst Rm,Rn shlr16 Rn tst.b #imm,@(R0,GBR) shlr2 Rn xor #imm,R0 shlr8 Rn xor Rm,Rn sleep xor.b #imm,@(R0,GBR) stc GBR,Rn xtrct Rm,Rn stc SR,Rn

8.16 SPARC Dependent Features

8.16.1 Options
8.16.2 Enforcing aligned data		Option to enforce aligned data
8.16.3 Floating Point
8.16.4 Sparc Machine Directives

8.16.1 Options